| Managing trace summaries to minimize stalls during postsilicon validation S Chandran, PR Panda, SR Sarangi, A Bhattacharyya, D Chauhan, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (6 …, 2017 | 13 | 2017 |
| Dhoom: Reusing design-for-debug hardware for online monitoring N Jindal, S Chandran, PR Panda, S Prasad, A Mitra, K Singhal, S Gupta, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 11 | 2019 |
| Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications S Chandran, P Kallurkar, P Gupta, SR Sarangi IEEE Transactions on Parallel and Distributed Systems 25 (5), 1166-1176, 2013 | 6 | 2013 |
| Extending trace history through tapered summaries in post-silicon validation S Chandran, PR Panda, D Chauhan, S Kumar, SR Sarangi 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 737-742, 2016 | 2 | 2016 |
| A generic implementation of barriers using optical interconnects S Chandran, E Peter, PR Panda, SR Sarangi 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 2 | 2016 |
| A Generic Implementation of Barriers Using Optical Interconnects S Chandran, E Peter, PR Panda, SR Sarangi 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 2 | 2016 |
| Area-Aware Cache Update Trackers for Postsilicon Validation S Chandran, SR Sarangi, PR Panda IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 2 | 2015 |
| Fundamental results for a generic implementation of barriers using optical interconnects S Chandran, E Peter, PR Panda, SR Sarangi arXiv preprint arXiv:1510.00220, 2015 | 1 | 2015 |
| Debug Data Reduction Techniques S Chandran, PR Panda Post-Silicon Validation and Debug, 211-229, 2019 | | 2019 |
| Space sensitive cache dumping for post-silicon validation S Chandran, SR Sarangi, PR Panda 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 497-502, 2013 | | 2013 |
