| Synthesis of ternary logic circuits using 2: 1 multiplexers C Vudadha, A Surya, S Agrawal, MB Srinivas IEEE transactions on circuits and systems I: regular papers 65 (12), 4313-4325, 2018 | 64 | 2018 |
| Design methodologies for ternary logic circuits CK Vudadha, MB Srinivas 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 192-197, 2018 | 31 | 2018 |
| 2: 1 Multiplexer based design for ternary logic circuits C Vudadha, S Katragadda, PS Phaneendra 2013 IEEE Asia Pacific conference on postgraduate research in …, 2013 | 31 | 2013 |
| Design of CNTFET-based ternary ALU using 2: 1 multiplexer based approach S Gadgil, C Vudadha IEEE Transactions on Nanotechnology 19, 661-671, 2020 | 26 | 2020 |
| CNFET based ternary magnitude comparator C Vudadha, PP Sai, V Sreehari, MB Srinivas 2012 International Symposium on Communications and Information Technologies …, 2012 | 26 | 2012 |
| Design of prefix-based optimal reversible comparator C Vudadha, PS Phaneendra, V Sreehari, SE Ahmed, NM Muthukrishnan, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 201-206, 2012 | 26 | 2012 |
| Design of high-speed and power-efficient ternary prefix adders using CNFETs C Vudadha, MB Srinivas IEEE Transactions on nanotechnology 17 (4), 772-782, 2018 | 23 | 2018 |
| Low-power self reconfigurable multiplexer based decoder for adaptive resolution flash adcs C Vudadha, G Makkena, MVS Nayudu, PS Phaneendra, SE Ahmed, ... 2012 25th International Conference on VLSI Design, 280-285, 2012 | 23 | 2012 |
| Encoder-based optimization of CNFET-based ternary logic circuits C Vudadha, S Rajagopalan, A Dusi, PS Phaneendra, MB Srinivas IEEE Transactions on Nanotechnology 17 (2), 299-310, 2018 | 22 | 2018 |
| An efficient design methodology for CNFET based ternary logic circuits C Vudadha, PS Phaneendra, MB Srinivas 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 17 | 2016 |
| Energy efficient design of CNFET-based multi-digit ternary adders C Vudadha, SP Parlapalli, MB Srinivas Microelectronics journal 75, 75-86, 2018 | 15 | 2018 |
| Design of CNFET based ternary comparator using grouping logic C Vudadha, PS Phaneendra, G Makkena, V Sreehari, NM Muthukrishnan, ... 2012 IEEE Faible Tension Faible Consommation, 1-4, 2012 | 15 | 2012 |
| An optimized design of reversible quantum comparator PS Phaneendra, C Vudadha, V Sreehari, MB Srinivas 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 13 | 2014 |
| A novel low power ternary multiplier design using cnfets H Sirugudi, S Gadgil, C Vudadha 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 11 | 2020 |
| Nanoscale devices: physics, modeling, and their application BK Kaushik CRC Press, 2018 | 8 | 2018 |
| A new design of an n-bit reversible arithmetic logic unit S Pal, C Vudadha, PS Phaneendra, S Veeramachaneni, S Mandalika 2014 Fifth International Symposium on Electronic System Design, 224-225, 2014 | 8 | 2014 |
| Design and analysis of reversible ripple, prefix and prefix-ripple hybrid adders C Vudadha, PS Phaneendra, SE Ahmed, V Sreehari, NM Muthukrishnan, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 225-230, 2012 | 8 | 2012 |
| A reconfigurable INC/DEC/2's complement/priority encoder circuit with improved decision block VC Kumar, PS Phaneendra, SE Ahmed, V Sreehari, NM Muthukrishnan, ... 2011 International symposium on electronic system design, 100-105, 2011 | 7 | 2011 |
| A unified architecture for BCD and binary adder/subtractor VC Kumar, PS Phaneendra, SE Ahmed, S Veeramachaneni, ... 2011 14th Euromicro Conference on Digital System Design, 426-429, 2011 | 7 | 2011 |
| Design of area optimised, energy efficient quaternary circuits using CNTFETs P Patel, N Doddapaneni, S Gadgil, C Vudadha 2019 Ieee International Symposium On Smart Electronic Systems (Ises …, 2019 | 6 | 2019 |
Sreehari VeeramachaneniVerified email at research.iiit.ac.in
