| Prevention of Train Accidents Using Wireless Sensor Networks N Sambamurthy, SH Ahammad ijera 3 (6), 1592-1597, 2013 | 17 | 2013 |
| Power optimised hybrid sorting-based median filtering N Sambamurthy, M Kamaraju International Journal of Digital Signals and Smart Systems,inderscience 4 (1 …, 2020 | 4 | 2020 |
| Design and Analysis of Parallel AES Encryption and Decryption Algorithm for Multi Processor Arrays N Sambamurthy, A Anusha IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 5 (1), 1-11, 2015 | 3* | 2015 |
| FPGA Implementation of PSO Based RGB-Y Filter N Sambamurthy, M Kamaraju International Journal of Advanced Trends in Computer Science and Engineering …, 2020 | 1 | 2020 |
| Efficient VLSI implementation of modular neural network based hybrid median filter. MK Nanduri Sambamurthy softcomputing, 2023 | | 2023 |
| High Performance Image Feature Detection and Matching N.Sambamurthy, Kamaraju.M Advances in Communications, Signal Processing, and VLSI 722 (https://doi.org …, 2021 | | 2021 |
| Area and Power efficient Comparator and swap switching network for Median filter N Sambamurthy, M Kamaraju Journal of solid state technology 63 (6), 17217-17227, 2020 | | 2020 |
| FPGA based Computational efficient and low power Median filter N Sambamurthy, M Kamaraju International Journal of critical reviews 7 (19), 8879-8893, 2020 | | 2020 |
| FPGA Based Optimized Reconfigurable Base-2 Constant Coefficient Multiplier Architecture for Image Filtering S NANDURI, M Kamaraju International Journal of Engineering and Advanced Technology (IJEAT), scopus …, 2019 | | 2019 |
| FPGA implementation of cordic multiplier based redundant floating point butterfly architecture for signal processing applications N Sambamurthy, M Kamaraju, AR Raju International Advanced Research Journal in Science, Engineering and …, 2016 | | 2016 |
| Power optimized codec for DSRC applications . N.Sambamurthy, Venkateswararao A, M.Kamaraju International Journal of Applied Engineering Research 10 (20), 41483-41489, 2015 | | 2015 |
| Hull Monitoring System for Submarine N Sambamurthy, M Kamaraju, KY Mala IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) 10 (2 …, 2015 | | 2015 |
| FPGA implementation of multiprocessor core Architecture for Embedded Concurrent Computing N Sambamurthy, M Kamaraju IET Digital Library, 2012 | | 2012 |
Dr.M.KamarajuProfessor of ECE, Gudlavalleru Engineering CollegeVerified email at gecgudlavalleru.ac.in
