Follow
jagadeeshkumar N
jagadeeshkumar N
teaching fellow
Verified email at mitindia.edu
Title
Cited by
Cited by
Year
A novel design of low power and high speed hybrid multiplier
N Jagadeeshkumar, D Meganathan
2017 Fourth International Conference on Signal Processing, Communication and …, 2017
62017
A systematic design of novel energy efficient 64-bit parallel-prefix adder
N Jagadeeshkumar, D Meganathan
INTERNATIONAL JOURNAL OF ELECTRONICS 108 (11), 1821-1842, 2021
22021
Approximate Compressor for Efficient Multiplication in Image Processing Applications
KP Akshay, N Jagadeeshkumar, MR Barusu, D Meganathan
2023 International Conference on Next Generation Electronics (NEleX), 1-6, 2023
2023
performance analysis of energy efficient carbon nanotube field effect transistor VLSI adder
jagadeeshkumar.n naveen kumar.p
international conference on computer science and engineering, 2013
2013
The system can't perform the operation now. Try again later.
Articles 1–4