Optimized VLSI Design of Squaring Multiplier Using Yavadunam Sutra Through Deficiency Bits Reduction DRRVV J. Sravana, K. S. Indrani, Sankeerth Mahurkar, M. Pranathi Advances in Signal Processing and Communication Engineering 929, pp 387–399, 2022 | 23* | 2022 |
Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer J Sravana, KS Indrani, M Saranya, PS Kiran, C Reshma, V Vijay Journal of VLSI circuits and systems 4 (2), 14-21, 2022 | 21 | 2022 |
A System for Controlling Positioning According To Movement Of Terminal In Wireless Communication Based On Ai Interface V Vijay, J Sravana, KS Indrani, G Ajitha, A Prashanth, K Nagaraja, ... The Patent Office Journal, 2021 | 19 | 2021 |
Optimized building of machine learning technique for thyroid monitoring and analysis KB Raju, PK Lakineni, KS Indrani, GMS Latha, K Saikumar 2021 2nd International Conference on Smart Electronics and Communication …, 2021 | 18 | 2021 |
Smart medicine pill box reminder with voice and display for emergency patients VB Sree, KS Indrani, GMS Latha Materials Today: Proceedings 33, 4876-4879, 2020 | 8 | 2020 |
QCA Based Universal Shift Register using 2 to 1 Mux and D flip-flop VV S Sushma,S Swathi,V Bindu sree,Sri Indrani Kotamraju,A Ashish Kumar | | 2021 |