| Digital fuzzy logic controller using VHDL SPJV Rani, P Kanagasabapathy, AS Kumar 2005 Annual IEEE India Conference-Indicon, 463-466, 2005 | 18 | 2005 |
| Multilayer perceptron neural network architecture using VHDL with combinational logic sigmoid function SPJV Rani, P Kanagasabapathy 2007 International Conference on Signal Processing, Communications and …, 2007 | 11 | 2007 |
| An area efficient, high-frequency digital built-in self-test for analogue to digital converter MS Sivakumar, SPJV Rani International Journal of Electronics 105 (8), 1319-1330, 2018 | 9 | 2018 |
| Design of linear ramp generator for ADC S Ashwini, MS Sivakumar, SPJV Rani 2017 Fourth International Conference on Signal Processing, Communication and …, 2017 | 9 | 2017 |
| Novel cat swarm optimization algorithm to enhance channel equalization DC Diana, JVR SP COMPEL-The international journal for computation and mathematics in …, 2017 | 8 | 2017 |
| Realization of deep learning based embedded soft sensor for bioprocess application NPSPJVR V.V.S. Vijaya Krishna Intelligent Automation and Soft Computing 32 (2), 781-794, 2022 | 7 | 2022 |
| Deep Learning based Soft Sensor for Bioprocess Application VVSV Krishna, N Pappa, SPJV Rani 2021 IEEE Second International Conference on Control, Measurement and …, 2021 | 7 | 2021 |
| An ADC BIST using on-chip ramp generation and digital ORA JVR SP Microelectronics Journal 81, 8-15, 2018 | 7 | 2018 |
| Modified inertia weight approach in PSO algorithm to enhance MMSE Equalization DC Diana, SPJV Rani 2021 Fourth International Conference on Electrical, Computer and …, 2021 | 6 | 2021 |
| Implementation of embedded soft sensor for bioreactor on Zynq processing system VVSV Krishna, N Pappa, SPJV Rani 2018 International conference on recent trends in electrical, control and …, 2018 | 5 | 2018 |
| An ADC BIST using on-chip ramp generation and digital ORA M Senthil Sivakumar, JVR SP Microelectronics Journal 81, 8-15, 2017 | 5 | 2017 |
| Area efficient high speed low power multiplier architecture for multirate filter design K Mariammal, SPJV Rani, T Kohila 2013 IEEE International Conference ON Emerging Trends in Computing …, 2013 | 5 | 2013 |
| Design of Neural Network on FPGA. SPJV Rani, P Kanagasabapathy ESA/VLSI, 509-512, 2004 | 5 | 2004 |
| Comparative analysis of the CMOS 180nm technology-based flash ADC designs using dynamic comparator and TIQ comparator MS Priya, MS Sivakumar, S Pulya 2019 2nd International Conference on Power and Embedded Drive Control …, 2019 | 4 | 2019 |
| Design of digital built-in self-test for analog to digital converter MS Sivakumar, SPJV Rani 2016 10th International Conference on Intelligent Systems and Control (ISCO …, 2016 | 4 | 2016 |
| Area and speed efficient implementation of symmetric FIR digital filter through reduced parallel LUT decomposed DA approach SC Prasanna, SPJV Rani Circuits and Systems 7 (08), 1379, 2016 | 4 | 2016 |
| Pipelined hardware design of self tuning controller with on-chip parameter estimator SPJV Rani International Journal of High Performance Systems Architecture 5 (3), 127-140, 2015 | 4 | 2015 |
| Reconfigurable architecture of RNS based high speed FIR filter JB Pari, SP Rani NISCAIR-CSIR, India, 2014 | 4 | 2014 |
| A fast on-chip adaptive genetic algorithm processor for evolutionary fir filter implementation using hardware–software co-design C Ranjith, SPJV Rani Journal of Circuits, Systems and Computers 29 (01), 2050014, 2020 | 3 | 2020 |
| Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms R Chandrasekharan, SPJV Rani International Journal of Bio-Inspired Computation 15 (1), 43-51, 2020 | 3 | 2020 |
M.Senthil SivakumarAsst.Professor of Electronics and Communication, IIIT TiruchirappalliVerified email at iiitt.ac.in
