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Nijwm Wary
Nijwm Wary
Assistant Professor IIT Bhubaneswar
Verified email at iitbbs.ac.in - Homepage
Title
Cited by
Cited by
Year
Current-mode full-duplex transceiver for lossy on-chip global interconnects
N Wary, P Mandal
IEEE Journal of Solid-State Circuits 52 (8), 2026-2037, 2017
272017
A study of discrete multitone modulation for wireline links beyond 100 Gb/s
B Vatankhahghadim, N Wary, J Bailey, AC Carusone
IEEE Open Journal of Circuits and Systems 2, 78-90, 2021
142021
Ultra-short-reach interconnects for die-to-die links: Global bandwidth demands in microcosm
B Dehlaghi, N Wary, TC Carusone
IEEE Solid-State Circuits Magazine 11 (2), 42-53, 2019
132019
Current-mode simultaneous bidirectional transceiver for on-chip global interconnects
N Wary, P Mandal
2015 6th Asia Symposium on Quality Electronic Design (ASQED), 19-24, 2015
132015
A low impedance receiver for power efficient current mode signalling across on-chip global interconnects
N Wary, P Mandal
AEU-International Journal of Electronics and Communications 68 (10), 969-975, 2014
112014
High‐speed energy‐efficient bi‐directional transceiver for on‐chip global interconnects
N Wary, P Mandal
IET Circuits, Devices & Systems 9 (5), 319-327, 2015
102015
Discrete multitone signalling for wireline communication
B Vatankhahghadim, N Wary, AC Carusone
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
62020
Design methodologies for low-jitter CMOS clock distribution
X Mo, J Wu, N Wary, TC Carusone
IEEE Open Journal of the Solid-State Circuits Society 1, 94-103, 2021
52021
Current-mode triline transceiver for coded differential signaling across on-chip global interconnects
N Wary, P Mandal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017
42017
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination
AR Chowdhury, N Wary, P Mandal
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
32019
Design and analysis of pvt invariant current reference in 65-nm cmos
N Maurya, N Wary
2022 IEEE 65th International Midwest Symposium on Circuits and Systems …, 2022
22022
Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnects
AR Chowdhury, N Wary, P Mandal
IET Circuits, Devices & Systems, 2020
22020
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects
PK Govindaswamy, N Wary, VSR Pasupureddi
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 852-856, 2022
12022
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects
PK Govindaswamy, N Wary, VSR Pasupureddi
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 857-861, 2022
12022
Current-integrating summer for DFE receiver with low common mode variation
PC Kondeti, SK Prusty, N Wary
Microelectronics Journal 123, 105408, 2022
12022
All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs
PW Chen, N Wary, L Wang, Q Wang, AC Carusone
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
12020
A regulated-cascode based current-integrating TIA RX with 1-tap speculative adaptive DFE
AR Chowdhury, N Wary, P Mandal
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems …, 2019
12019
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects
J Singh, N Wary, P Mandal
2024 37th International Conference on VLSI Design and 2024 23rd …, 2024
2024
Differential Evolution Based Adaptation Algorithm for Multi-Stage Continuous Time Linear Equalizer
SK Prusty, SP Dash, VK Surya, N Wary
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2023
2023
Energy Efficient Integrated Summer and Latch Based DFE With Reduced Tap Loading
SK Prusty, VK Surya, N Wary
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
2023
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