| Efficient capacity image steganography by using wavelets Yedla Dinesh, Addanki Purna Ramesh International Journal of Engineering Research and Applications 2 (1), 251-259, 2012 | 21* | 2012 |
| An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog Addanki Purna Ramesh, A V N Tilak, A M Prasad 2013 International Conference on Emerging Trends in VLSI, Embedded System …, 2013 | 20 | 2013 |
| Pipelined architecture of 2D-DCT, quantization and zigzag process for JPEG image compression using VHDL T Pradeepthi, Addanki Purna Ramesh International Journal of VLSI Design & Communication Systems 2 (3), 99, 2011 | 19 | 2011 |
| Automatic detection of human and Energy saving based on Zigbee Communication Chinnam Sujana, P Gopala Reddy, Addanki Purna Ramesh International journal on computer science and engineering 3 (6), 2346-2353, 2011 | 13 | 2011 |
| Implementation of dadda and array multiplier architectures using tanner tool Addanki Purna Ramesh International Journal of Computer Science & Engineering Technology (IJCSET) 2, 8, 2011 | 11 | 2011 |
| An FPGA Based High Speed IEEE - 754 Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog Addanki Purna Ramesh, A.V.N.Tilak, A.M.Prasad International Journal of Advanced Science and Technology (IJAST) 52, 61-74, 2013 | 10* | 2013 |
| Efficient implementation of 16-bit multiplier-accumulator using radix-2 modified booth algorithm and SPST adder using Verilog Addanki Purna Ramesh, A V N Tilak, A M Prasad International Journal of VLSI Design & Communication Systems 3 (3), 107, 2012 | 8 | 2012 |
| FPGA based design and implementation of higher order FIR filter using improved DA algorithm Addanki Purna Ramesh, G Nagarjuna, G Siva Raam International Journal of Computer Applications 35 (9), 45-54, 2011 | 7 | 2011 |
| Asynchronous Single Precision Floating Point Multiplier using Verilog HDL Koneru Priyanka, Tinnanti Sreenivasu, Addanki Purna Ramesh IJ of Advanced Research in Electronics and Communication Engineering, 2013 | 6 | 2013 |
| Novel Design of Multiplexer and Demultiplexer using Reversible Logic Gates Addanki Purna Ramesh, Nune Veerendra Nath International Journal of Engineering &Technology (UAE) ISSN: 2227-524X 7 (3 …, 2018 | 5* | 2018 |
| Floating point multiplier using Canonical Signed Digit D.Harini Sharma, Addanki Purna Ramesh International Journal Of Advanced Research in Electronics and Communication …, 2013 | 5* | 2013 |
| Implementation of Low Power High Speed Adder’s using GDI Logic Addanki Purna Ramesh International Journal of Innovative Technology and Exploring Engineering …, 2019 | 4* | 2019 |
| Implementation of Integer Square Root Addanki Purna Ramesh, I.Jayaram Kumar International Journal of Engineering Science and Innovative Technology …, 2015 | 4* | 2015 |
| Dual Image Signature Method using DWT and SVD in YCbCr Colour Space Addanki Purna Ramesh, M Dheeraj International Journal of Innovative Technology and Exploring Engineering …, 2019 | 3* | 2019 |
| Implementation of sequential circuit using feynman and fredkin reversible logic gates K Bala Krishna, Addanki Purna Ramesh Journal of Physics: Conference Series 1228 (1), 012047, 2019 | 3 | 2019 |
| A Dual Security Scheme Based On DWT For Personnel Authentication P Sivananthamaitrey, V Venkata Krishna, Addanki Purna Ramesh, ... International Journal of Engineering and Advanced Technology (IJEAT) ISSN …, 2019 | 2 | 2019 |
| Implementation of low power carry skip adder using reversible logic Addanki Purna Ramesh International Journal of Recent Technology and Engineering (IJRTE) ISSN …, 2019 | 2* | 2019 |
| Novel design of multiplexers using adiabatic logic Addanki Purna Ramesh International Journal of Engineering & Technology 7 (4), 5331-5339, 2018 | 2 | 2018 |
| FPGA based implementation of high speed double precision floating point multiplier with tiling technique using Verilog Addanki Purna Ramesh, A V N Tilak, A M Prasad International Journal of Computer Applications 975, 8887, 2012 | 2 | 2012 |
| An FPGA Based High Performance IEEE - 754 Digit Recurrence Floating Point Double Precision Divisor Using Verilog Addanki Purna Ramesh, A V N Tilak, A M Prasad International Journal of Advanced Science and Technology (IJAST) 48, 125-132, 2012 | 2* | 2012 |
