| A 76.6-dB-SNDR 50-MHz-BW 29.2-mW multi-bit CT sturdy MASH with DAC non-linearity tolerance L Qi, A Jain, D Jiang, SW Sin, RP Martins, M Ortmanns IEEE Journal of Solid-State Circuits 55 (2), 344-355, 2019 | 47 | 2019 |
| 20.5 A 76.6 dB-SNDR 50MHz-BW 29.2 mW noise-coupling-assisted CT sturdy MASH ΔΣ modulator with 1.5 b/4b quantizers in 28nm CMOS L Qi, A Jain, D Jiang, SW Sin, RP Martins, M Ortmanns 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 336-338, 2019 | 20 | 2019 |
| A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation D Jiang, L Qi, SW Sin, F Maloberti, RP Martins IEEE Journal of Solid-State Circuits 56 (8), 2375-2387, 2021 | 14 | 2021 |
| A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS D Jiang, L Qi, SW Sin, F Maloberti, RP Martins 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 13 | 2020 |
| Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs D Jiang, SW Sin, L Qi, G Wang, RP Martins IEEE Open Journal of the Solid-State Circuits Society 1, 129-139, 2021 | 5 | 2021 |
| Reconfigurable mismatch‐free time‐interleaved bandpass sigma–delta modulator for wireless communications D Jiang, SW Sin, SP U, RP Martins, F Maloberti Electronics Letters 53 (7), 506-508, 2017 | 5 | 2017 |
| Advanced Architecture Alternatives for Time-Interleaved Delta-Sigma Modulators D Jiang PQDT-Global, 2021 | | 2021 |
| A 107dB DR, 106dB SNDR Sigma-Delta ADC Using a Charge-Pump Integrator for Audio Application D JIANG, J LIANG | | 2014 |
