| Shared Reed‐Muller Decision Diagram Based Thermal‐Aware AND‐XOR Decomposition of Logic Circuits A Das, SN Pradhan VLSI Design 2016 (1), 3191286, 2016 | 14 | 2016 |
| Thermal aware FPRM based AND-XOR network synthesis of logic circuits A Das, SN Pradhan 2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015 | 14 | 2015 |
| Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion A Das, SN Pradhan International Journal of Intelligent Systems and Applications 10 (12), 35-46, 2018 | 12 | 2018 |
| An elitist area-power density trade-off in VLSI floorplan using genetic algorithm A Das, SR Choudhury, BK Kumar, SN Pradhan 2012 7th International Conference on Electrical and Computer Engineering …, 2012 | 12 | 2012 |
| Design Time Temperature Reduction in Mixed Polarity Dual Reed-Muller Network: a NSGA-II Based Approach A Das, SN Pradhan Advances in Electrical and Computer Engineering 20 (01), 99-104, 2020 | 11 | 2020 |
| NSGA-II based thermal-aware mixed polarity dual Reed–Muller network synthesis using parallel tabular technique A Das, YC Hareesh, SN Pradhan Journal of Circuits, Systems and Computers 29 (15), 2020008, 2020 | 10 | 2020 |
| Area, power and temperature optimization during binary decision diagram based circuit synthesis A Das, A Debnath, SN Pradhan 2017 Devices for Integrated Circuit (DevIC), 778-782, 2017 | 9 | 2017 |
| Thermal aware output polarity selection of programmable logic arrays A Das, SN Pradhan International Conference on Electronic Design, Computer Networks & Automated …, 2015 | 9 | 2015 |
| An elitist non-dominated multi-objective genetic algorithm based temperature aware circuit synthesis A Das, SN Pradhan International Journal of Interactive Multimedia and Artificial Intelligence …, 2020 | 7 | 2020 |
| A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously A Bhattacharjee, A Das, DK Sahu, SN Pradhan, K Das Microelectronics Reliability 144, 114979, 2023 | 4 | 2023 |
| Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation A Das, SN Pradhan Recent Advances in Electrical & Electronic Engineering 12 (1), 30 - 39, 2019 | 4 | 2019 |
| Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis A Das, V Kumar Singh, S Nath Pradhan International Journal of Circuit Theory and Applications 50 (6), 2271-2286, 2022 | 3 | 2022 |
| Reduced ordered binary decision diagram-based combinational circuit synthesis for optimising area, power and temperature A Das, A Debnath, SN Pradhan International Journal of Nanoparticles 11 (2), 94-112, 2019 | 2 | 2019 |
| Low Power Design of 16-Bit Synchronous Counter by Introducing Effective Clock Monitoring Circuits VK Singh, A Nag, A Das, SN Pradhan Songklanakarin Journal of Science and Technology 45 (4), 464-469, 2023 | | 2023 |
| Temperature Aware Bi-partitioning Multi-level Logic Synthesis A Das, VK Singh, SN Pradhan Soft Computing: Theories and Applications: Proceedings of SoCTA 2022, 423-430, 2023 | | 2023 |
sambhu Nath PradhanProfessor, NIT AgartalaVerified email at nita.ac.in
