| Power-Aware Alternative Adder Cell Structure Using Swing Restored Complementary Pass Transistor Logic at 45nm Technology SS T. Bhagyalaxmi, S. Rajendar Elsevier Procedia Material Science 10 (1), 789-792, 2015 | 10* | 2015 |
| Design of Low Power Adaptive Pulse TriggeredFlip-Flop Using Modified Clock Gating Schemeat 90nm Technology RN Krishna Kavali, S. Rajendar Elsevier Procedia Material Science 10 (1), 323-330, 2015 | 8* | 2015 |
| Design of noise immune subthreshold circuits using dynamic threshold Schmitt trigger logic R Sandiri, Y Chimata, Y Nalamasa, P Arra 2022 IEEE Region 10 Symposium (TENSYMP), 1-6, 2022 | 6 | 2022 |
| Design of low power memory architecture using 4T content addressable memory cell P Ramakrishna, S Rajendar, N Malladhi 2017 4th International Conference on Advanced Computing and Communication …, 2017 | 4 | 2017 |
| Design of low power pulsed flip-flop using sleep transistor scheme GM Rao, S Rajendar 2013 2nd International Conference on Advances in Electrical Engineering …, 2013 | 4 | 2013 |
| Design of a parallel self-timed adder by using transmission gate logic style S Bhargavi, S Rajendar 2017 4th International Conference on Advanced Computing and Communication …, 2017 | 3 | 2017 |
| Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic GM Rao, S Rajendar International Journal of Computer Applications 80 (15), 2013 | 3 | 2013 |
| A novel high performance design of memory architecture using modified 4T CAM cell S Rajendar, P Ramakrishna 2017 International Conference on Inventive Communication and Computational …, 2017 | 2 | 2017 |
| A novel low power dynamic memory architecture using single supply 3t gain cell M Nagarjuna, G Mamatha, S Rajendar 2017 IEEE 7th International Advance Computing Conference (IACC), 440-443, 2017 | 2 | 2017 |
| A SIMULATION BASED DECISION-MAKING SUPPORT APPROACH FOR MACHINE-BUILDING PLANTS INVESTMENT PROJECTS ESTIMATION OF EFFICIENCY VZ MIKHAIL, YG DREVS, N ABDULLAH, AJ MARZANAH, ... Journal of Theoretical and Applied Information Technology 81 (3), 2015 | 2 | 2015 |
| Notice of Removal: A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique K Kavali, S Rajendar, PV Bhargava 2015 International Conference on Electrical, Electronics, Signals …, 2015 | 2 | 2015 |
| Performance Analysis of Alternate Repeaters for On-Chip Interconnections in Nanometer Technologies RN S. Rajendar, P. Chandrasekhar, M. Asha Rani Elsevier Procedia Material Science 10 (1), 344-352, 2015 | 2* | 2015 |
| Design and Implementation of a Floating Point ALU on a STRATIX-III FPGA BUV Prashanth, C Padmini, S Rajendar International Journal of Computer Applications 55 (2), 2012 | 2 | 2012 |
| The State-of-the-art Energy Management Strategy in Hybrid Electric Vehicles for Real-time Optimization S Dasi, R Sandiri, T Anuradha, TS Sri, S Majji, K Murugan 2023 International Conference on Inventive Computation Technologies (ICICT …, 2023 | 1 | 2023 |
| Towards Human-Like Robotic Grasping for Industrial Applications Using Computer Vision S Prasada Rao Borra, R Sandiri, P Nalajala, S Majji, C Saravanakumar, ... International Conference on Intelligent Sustainable Systems, 173-181, 2023 | 1 | 2023 |
| A Novel Low Power High Dynamic Threshold Swing Limited Repeater Insertion for On-Chip Interconnects S Rajendar, P Chandrasekhar, MA Rani, A Divya International Journal of VLSI Design & Communication Systems 5 (6), 63, 2014 | 1 | 2014 |
| A CHARGE RECYCLING THREE-PHASE DUAL-RAIL PRE-CHARGE LOGIC BASED FLIP-FLOP K Mounika, S Rajendar, R Naresh International Journal of VLSI Design & Communication Systems 5 (6), 35, 2014 | 1 | 2014 |
| Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology TB Laxmi, S Rajendar, YP Rangaiah 2014 International Conference on Advances in Computing, Communications and …, 2014 | 1 | 2014 |
| Integration of bus specific clock gating and power gating M Nagarjuna, BN Reddy, S Rajendar power 12, 16, 2014 | 1 | 2014 |
| Design, validation and correlation of characterized SODIMM modules supporting DDR3 memory interface V Harini, S Rajendar Journal of Electronics and Communication Engineering 6, 5, 0 | 1 | |
