| Design of CNTFET-based 2-bit ternary ALU for nanoelectronics SL Murotiya, A Gupta International Journal of Electronics 101 (9), 1244-1257, 2014 | 52 | 2014 |
| Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology SL Murotiya, A Gupta International Journal of Electronics 103 (5), 913-927, 2016 | 39 | 2016 |
| Design of high speed ternary full adder and three-input XOR circuits using CNTFETs SL Murotiya, A Gupta 2015 28th International Conference on VLSI Design, 292-297, 2015 | 36 | 2015 |
| Low-Latency Median Filter Core for Hardware Implementation of 5-by-5 Median Filtering AAAG 29. Vineet Kumar IET Image Processing, 2017 | 23 | 2017 |
| A novel design of ternary full adder using CNTFETs SL Murotiya, A Gupta Arabian Journal for Science and Engineering 39, 7839-7846, 2014 | 22 | 2014 |
| A holistic framework for crime prevention, response, and analysis with emphasis on women safety using technology and societal participation MV Shenoy, S Sridhar, G Salaka, A Gupta, R Gupta IEEE Access 9, 66188-66207, 2021 | 21 | 2021 |
| Ultra low power MUX based compressors for wallace and dadda multipliers in sub-threshold regime P Gupta, A Gupta, A Asati American Journal of Engineering and Applied Sciences 8 (4), 702, 2015 | 19 | 2015 |
| Iris localization based on integro-differential operator for unconstrained infrared iris images V Kumar, A Asati, A Gupta 2015 International Conference on Signal Processing, Computing and Control …, 2015 | 18 | 2015 |
| Design of a fully differential two-stage cmos op-amp for high gain, high bandwidth applications RS Parihar, A Gupta IEEE J Microchip Technol Inc 40 (1), 32-38, 2006 | 17 | 2006 |
| Performance evaluation of CNTFET-based SRAM cell design SL Murotiya, A Matta, A Gupta International Journal of Electrical and Electronics Engineering 2 (1), 78-83, 2012 | 16 | 2012 |
| Design explorations of VLSI arithmetic circuits A Gupta BITS Pilani, Pilani Campus, 2002 | 16 | 2002 |
| A low power low noise amplifier for biomedical applications D Dubey, A Gupta 2015 IEEE International Conference on Electrical, Computer and Communication …, 2015 | 15 | 2015 |
| On-chip resistors can make a stable current reference N Bhattar, A Gupta IEEE Potentials 27 (1), 31-36, 2008 | 15 | 2008 |
| Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation V Kumar, A Asati, A Gupta IET Image Processing 12 (10), 1753-1761, 2018 | 14 | 2018 |
| Hardware accelerators for iris localization V Kumar, A Asati, A Gupta Journal of Signal Processing Systems 90, 655-671, 2018 | 14 | 2018 |
| Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images V Kumar, A Asati, A Gupta Engineering Science and Technology, an International Journal 20 (2), 694-704, 2017 | 14 | 2017 |
| Design and performance evaluation of a low transistor ternary CNTFET SRAM cell P Srinivasan, AS Bhat, SL Murotiya, A Gupta 2015 International Conference on Electronic Design, Computer Networks …, 2015 | 14 | 2015 |
| Novel design of ternary magnitude comparator using CNTFETs SL Murotiya, A Gupta, S Vasishth 2014 Annual IEEE India Conference (INDICON), 1-4, 2014 | 13 | 2014 |
| An analysis of digital image compression technique in image processing A Gupta, P Narwal, V Kumar International Journal of Advanced Science and Technology 28 (20), 1261-1265, 2020 | 12 | 2020 |
| Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images. V Kumar, A Asati, A Gupta International Journal of Electrical & Computer Engineering (2088-8708) 6 (4), 2016 | 11 | 2016 |
Nitin ChaturvediBITS, Pilani, IndiaVerified email at pilani.bits-pilani.ac.in
