| A high performance on-chip segmented bus architecture using dynamic bridge-by-pass technique SH Chitra, A Kandaswamy 2010 5th International Conference on Industrial and Information Systems, 249-254, 2010 | 3 | 2010 |
| Razor flip-flop based Detector/Corrector System for Correcting Timing violations in Digital Circuits SH Chitra, R Vaidhehi, S Mohandass Journal of Physics: Conference Series 1917 (1), 012015, 2021 | 1 | 2021 |
| Investigating the performance of CNFET using 10T SET D-Flip flop E Raguvaran, KSN Vishnu, SH Chitra 2012 International Conference on Computer Communication and Informatics, 1-5, 2012 | 1 | 2012 |
| Design of IP Core for ZigBee Transmitter and ECG Signal Analysis K Sarvesh, S Hema Chitra, S Mohandass Mobile Computing and Sustainable Informatics: Proceedings of ICMCSI 2021 …, 2022 | | 2022 |
| VLSI Implementation of RSA Cryptography using Fractional Chebyshev Polynomials SH Chitra, R Yogeshwaran Asian Journal of Research in Social Sciences and Humanities 7 (3), 43-60, 2017 | | 2017 |
| Design and Implementation of a Pipelined Instruction Decoder for an ASIP DSP SS Rekha, SH Chitra, A Kandaswamy Procedia engineering 38, 2237-2243, 2012 | | 2012 |
| Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders S Hema Chitra, RP Bo Rajalin | | |
| High Speed Low Error Approximate Adder Using Hybrid Bit Truncation S Hema Chitra | | |
