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Cited by
All
Since 2019
Citations
4
4
h-index
1
1
i10-index
0
0
0
2
1
2019
2020
2021
2022
2023
1
1
2
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Veerendra Satyavolu
Assistant Professor
Verified email at sasi.ac.in
VLSI
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Design and realization of CMOS circuits using dual integrated technique to reduce power dissipation
M Kamaraju, V Satyavolu, KL Kishore
2015 International Conference on Signal Processing and Communication …
, 2015
4
2015
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