Follow
Zhe Lin
Zhe Lin
Assistant Professor, the School of Integrated Circuits, Sun Yat-sen University, China
Verified email at mail.sysu.edu.cn - Homepage
Title
Cited by
Cited by
Year
PanGu-: Large-scale Autoregressive Pretrained Chinese Language Models with Auto-parallel Computation
W Zeng, X Ren, T Su, H Wang, Y Liao, Z Wang, X Jiang, ZZ Yang, K Wang, ...
arXiv preprint arXiv:2104.12369, 2021
1822021
Pre-training on Large-Scale Heterogeneous Graph
X Jiang, T Jia, Y Fang, C Shi, Z Lin, H Wang
Proceedings of the 27th ACM SIGKDD Conference on Knowledge Discovery & Data …, 2021
362021
HL-Pow: A learning-based power modeling framework for high-level synthesis
Z Lin, J Zhao, S Sinha, W Zhang
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 574-580, 2020
252020
Towards efficient and scalable acceleration of online decision tree learning on FPGA
Z Lin, S Sinha, W Zhang
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
172019
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
122018
Powergear: Early-stage power estimation in FPGA HLS via heterogeneous edge-centric GNNs
Z Lin, Z Yuan, J Zhao, W Zhang, H Wang, Y Tian
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
112022
Hard-odt: Hardware-friendly online decision tree learning algorithm and system
Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
112020
Decision tree based hardware power monitoring for run time dynamic power management in FPGA
Z Lin, W Zhang, S Sharad
2017 27th International Conference on Field Programmable Logic and …, 2017
102017
Scalable light-weight integration of FPGA based accelerators with chip multi-processors
Z Lin, S Sinha, H Liang, L Feng, W Zhang
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 152-162, 2017
62017
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
Z Lin, T Liang, J Zhao, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
22023
Mars: Exploiting multi-level parallelism for dnn workloads on adaptive multi-accelerator systems
G Shen, J Zhao, Z Wang, Z Lin, W Ding, C Wu, Q Chen, M Guo
2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023
12023
Improving GPU Energy Efficiency through an Application-transparent Frequency Scaling Policy with Performance Assurance
Y Zhang, Q Wang, Z Lin, P Xu, B Wang
Proceedings of the Nineteenth European Conference on Computer Systems, 769-785, 2024
2024
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
C Su, L Du, T Liang, Z Lin, M Wang, S Sinha, W Zhang
Proceedings of the 2024 ACM/SIGDA International Symposium on Field …, 2024
2024
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
M Gao, J Zhao, Z Lin, M Guo
arXiv preprint arXiv:2401.08696, 2024
2024
Learning-based power modeling for FPGA: from design time to run time
Z Lin
Hong Kong University of Science and Technology, 2019
2019
The system can't perform the operation now. Try again later.
Articles 1–15