| Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi IEEE Transactions on Electron Devices 47 (4), 789-796, 2000 | 71 | 2000 |
| A new charge-control model for single-and double-heterojunction bipolar transistors CD Parikh, FA Lindholm IEEE transactions on electron devices 39 (6), 1303-1311, 1992 | 59 | 1992 |
| Space-charge region recombination in heterojunction bipolar transistors CD Parikh, FA Lindholm IEEE transactions on electron devices 39 (10), 2197-2205, 1992 | 47 | 1992 |
| A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi IEEE Transactions on Electron Devices 47 (1), 171-177, 2000 | 46 | 2000 |
| A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi IEEE Transactions on Electron Devices 47 (1), 171-177, 2000 | 46 | 2000 |
| Modeling of the CoolMOS/sup TM/transistor-Part I: Device physics BJ Daniel, CD Parikh, MB Patil IEEE Transactions on Electron Devices 49 (5), 916-922, 2002 | 42 | 2002 |
| A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs S Mahapatra, CD Parikh, J Vasi, VR Rao, CR Viswanathan Solid-State Electronics 43 (5), 915-922, 1999 | 34 | 1999 |
| Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/using theory of novel voltage sustaining layer PN Kondekar, CD Parikh, MB Patil 2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference …, 2002 | 30 | 2002 |
| Modeling of the CoolMOS/sup TM/transistor. II. DC model and parameter extraction BJ Daniel, CD Parikh, MB Patil IEEE Transactions on Electron Devices 49 (5), 923-929, 2002 | 21 | 2002 |
| 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric S Mahapatra, VR Rao, KNM Rani, CD Parikh, J Vasi, B Cheng, M Khare, ... 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 1999 | 18 | 1999 |
| Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/MNSFETs S Mahapatra, VR Rao, B Cheng, M Khare, CD Parikh, JCS Woo, JM Vasi IEEE Transactions on Electron Devices 48 (4), 679-684, 2001 | 15 | 2001 |
| A new" multifrequency" charge pumping technique to profile hot-carrier-induced interface-state density in nMOSFET's S Mahapatra, CD Parikh, J Vasi IEEE Transactions on Electron Devices 46 (5), 960-967, 1999 | 15 | 1999 |
| A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping S Mahapatra, VR Rao, CD Parikh, J Vasi, B Cheng, JCS Woo Microelectronic engineering 48 (1-4), 193-196, 1999 | 13 | 1999 |
| High performance operational amplifier with 90db gain in scl 180nm technology S Padma, S Das, S Sen, CD Parikh 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-5, 2020 | 12 | 2020 |
| Analysis and design of superjunction power MOSFET: CoolMOS/spl trade/for improved on resistance and breakdown voltage using theory of novel voltage sustaining layer PN Kondekar, MB Patil, CD Parikh 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No …, 2002 | 12 | 2002 |
| Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET VR Bhumireddy, KA Shaik, A Amara, S Sen, CD Parikh, D Nagchoudhuri, ... 2013 IEEE International Conference on Circuits and Systems (ICCAS), 1-4, 2013 | 11 | 2013 |
| A compact model for the N-well resistor CD Parikh, RM Patrikar Solid-State Electronics 43 (3), 683-685, 1999 | 11 | 1999 |
| Modelling of a depletion-mode MOSFET CD Parikh, J Vasi Solid-state electronics 30 (7), 699-703, 1987 | 10 | 1987 |
| Deterministic digital calibration technique for 1.5 bits/stage pipelined and algorithmic ADCs with finite op-amp gain and large capacitance mismatches C Ramamurthy, CD Parikh, S Sen Circuits, Systems, and Signal Processing 40 (8), 3684-3702, 2021 | 9 | 2021 |
| A new delay model and geometric programming-based design automation for latched comparators A Purushothaman, CD Parikh Circuits, Systems, and Signal Processing 34, 2749-2764, 2015 | 9 | 2015 |
