Follow
Durga G
Durga G
Verified email at ssn.edu.in
Title
Cited by
Cited by
Year
Implementation of Hough Transform for image processing applications
L Chandrasekar, G Durga
2014 International Conference on Communication and Signal Processing, 843-847, 2014
222014
SET analysis of silicon nanotube FET
GD Jayakumar, R Srinivasan
Journal of Computational Electronics 16, 307-315, 2017
142017
Design of low power and high speed ripple carry adder
S Archana, G Durga
2014 International Conference on Communication and Signal Processing, 939-943, 2014
132014
Performance optimization of bulk junctionless FinFETs through work function engineering
R Bharathi, G Durga, NV Kumar, KK Nagarajan, R Srinivasan
2014 International Conference on Circuits, Power and Computing Technologies …, 2014
72014
Silicon nanotube SRAM and its SEU reliability
GD Jayakumar, R Srinivasan
Superlattices and Microstructures 106, 129-138, 2017
42017
Single event transient analysis on junctionless silicon nanotube field effect transistor
G Durga, V Balamurugan, R Srinivasan
2017 International Conference on Information Communication and Embedded …, 2017
32017
Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata
RKR Venna, GD Jayakumar
The Journal of Supercomputing 79 (2), 1908-1925, 2023
22023
Design of Digital Filter using Low Power and Area Efficient SQRT CSLA
GD R. Subha
IJCA Proceedings on National Conference on VLSI and Embedded Systems 2 (Feb …, 2013
22013
Reconfigurable FET-Based Tunable Ring Oscillator and Its Single Event Effect Performance
G Durga Jayakumar, S Kumar Pal, R Srinivasan
Journal of Circuits, Systems and Computers 31 (18), 2240008, 2022
12022
Numerical study on SEU performance of strain engineered 6T-SRAM cells
N Vinodhkumar, G Durga, S Muthumanickam
Journal of Circuits, Systems and Computers 31 (02), 2250034, 2022
12022
Heavy-ion irradiation study in SiNT FET inverter chain using 3D-TCAD simulation
G Durga, R Srinivasan
2020 5th IEEE International Conference on Emerging Electronics (ICEE), 1-6, 2020
12020
Design of 50–75 GHz V-band low power and high gain down-conversion mixer
K Suriya, G Durga
2014 International Conference on Communication and Signal Processing, 1625-1629, 2014
12014
Soft error study on junctionless silicon nanotube FET based 6T SRAM cell
G Durga, R Srinivasan
Journal of Physics: Conference Series 1706 (1), 012027, 2020
2020
Radiation and thermal study on Defensive MOSFET
MB Ramprasath, V Raviteja, G Durga, R Srinivasan
2020 5th IEEE International Conference on Emerging Electronics (ICEE), 1-4, 2020
2020
Design of 8 bit Vedic Multiplier using GDI Logic
GD U M Sharmili
ICRDET'20, 2020
2020
Understanding the impact of Heavy-Ion Induced Single Event Upsets in Phase Change Memory
AM Suresh Durai, Durga Jayakumar, Srinivasn Raj
European Phase Change and Ovonic Symposium (EPCOS 2018), 155-157, 2018
2018
Performance Analysis of Single Event Double Upset Immune D and S-R Flip flops
GDMM Rino
WSEAS Transactions on Electronics 9 (7), 61-68, 2018
2018
Design and Implementation of Residue adder and BCD adder using multi output domino logic based CLA
GD J.Abdulrahumaan
International Conference on Technological Convergence For Information …, 2015
2015
VLSI implementation of double precision decimal floating point arithmetic unit
GD Gowtham V.R
International Conference On Technological Convergence For Information …, 2015
2015
VLSI implementation of double precision decimal floating point multiplier unit
DG Gowtham V.R
Journal of Science and Innovative Engineering&Technology 2 (May), 61, 2015
2015
The system can't perform the operation now. Try again later.
Articles 1–20