J DINESH REDDY JEERU

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Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
System Verilog Based SOC Verification Environment for FLASH MEMORY JD Reddy VCASAN-2013, 2013		2013
A SURVEY ON SECURITY MEASURES IMPLEMENTED TO DETECT BURGLARY AT THE ATM International Journal of Research in Engineering and Technology, 2012		2012
Memory Controllers: A comparative study of SDRAM and DDR SDRAM Controller NC Pavankumar, JD Reddy
Domino CMOS Implementation of Power Optimized and High Performance CLA adder KK Reddy, JD Reddy

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Articles 1–4

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