| Novel attributes of a dual material gate nanoscale tunnel field-effect transistor S Saurabh, MJ Kumar IEEE transactions on Electron Devices 58 (2), 404-410, 2010 | 464 | 2010 |
| Fundamentals of tunnel field-effect transistors S Saurabh, MJ Kumar CRC press, 2016 | 193 | 2016 |
| Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis S Saurabh, MJ Kumar Japanese Journal of Applied Physics 48 (6R), 064503, 2009 | 158 | 2009 |
| Resistive random access memory: a review of device challenges V Gupta, S Kapur, S Saurabh, A Grover IETE Technical Review 37 (4), 377-390, 2020 | 86 | 2020 |
| Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis S Garg, S Saurabh Superlattices and Microstructures 113, 261-270, 2018 | 83 | 2018 |
| Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability S Saurabh, MJ Kumar IEEE Transactions on Device and Materials Reliability 10 (3), 390-395, 2010 | 78 | 2010 |
| Realizing logic functions using single double-gate tunnel FETs: A simulation study S Banerjee, S Garg, S Saurabh IEEE Electron Device Letters 39 (5), 773-776, 2018 | 30 | 2018 |
| Improving the scalability of SOI-based tunnel FETs using ground plane in buried oxide S Garg, S Saurabh IEEE Journal of the Electron Devices Society 7, 435-443, 2019 | 29 | 2019 |
| Implementing logic functions using independently-controlled gate in double-gate tunnel FETs: investigation and analysis S Garg, S Saurabh IEEE Access 7, 117591-117599, 2019 | 23 | 2019 |
| Modeling multiple-input switching in timing analysis using machine learning OVSS Ram, S Saurabh IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 16 | 2020 |
| Dopingless 1T DRAM: Proposal, design, and analysis A James, S Saurabh IEEE Access 7, 88960-88969, 2019 | 13 | 2019 |
| A practical methodology to compress technology libraries using recursive polynomial representation S Saurabh, P Mittal 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 11 | 2018 |
| Method and apparatus for comprehension of common path pessimism during timing model extraction S Saurabh, N Kumar, I Keller US Patent 8,938,703, 2015 | 11 | 2015 |
| Timing closure problem: Review of challenges at advanced process nodes and solutions S Saurabh, H Shah, S Singh IETE Technical Review, 2018 | 10 | 2018 |
| Implementing a ternary inverter using dual-pocket tunnel field-effect transistors A Gupta, S Saurabh IEEE Transactions on Electron Devices 68 (10), 5305-5310, 2021 | 9 | 2021 |
| Implementation of Boolean functions using tunnel field-effect transistors S Garg, S Saurabh IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020 | 9 | 2020 |
| Method and apparatus for efficient generation of compact waveform-based timing models S Saurabh, N Kumar US Patent 9,727,676, 2017 | 9 | 2017 |
| Realizing XOR and XNOR functions using tunnel field-effect transistors S Garg, S Saurabh IEEE Journal of the Electron Devices Society 8, 1001-1009, 2020 | 8 | 2020 |
| Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs S Saurabh, N Kumar US Patent 10,255,403, 2019 | 8 | 2019 |
| Exploiting within-channel tunneling in a nanoscale tunnel field-effect transistor S Garg, S Saurabh IEEE Open Journal of Nanotechnology 1, 100-108, 2020 | 7 | 2020 |
Mamidala Jagadesh Kumar.Indian Institute of Technology Delhi; Chairman, UGCVerified email at ee.iitd.ac.in
