| Design of Diffierential TG based 8T SRAM Cell for Ultralow Power Applications AI C Roy Microsystem Technologies, 1-12, 0 | 23* | |
| Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region C Roy, A Islam Microelectronics reliability 120, 114126, 2021 | 19 | 2021 |
| Comparative analysis of various 9T SRAM cell at 22-nm technology node C Roy, A Islam 2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015 | 17 | 2015 |
| Power-aware sourse feedback single-ended 7T SRAM cell at nanoscale regime C Roy, A Islam Microsystem Technologies 25, 1783-1791, 2019 | 15 | 2019 |
| Characterization of single-ended 9T SRAM cell C Roy, A Islam Microsystem Technologies 26, 1591-1604, 2020 | 14 | 2020 |
| Design of a stable read-decoupled 6T SRAM cell at 16-nm technology node N Anand, A Sinha, C Roy, A Islam 2015 IEEE international conference on computational intelligence …, 2015 | 14 | 2015 |
| TG based 2T2M RRAM using memristor as memory element C Roy, A Islam Indian Journal of Science and Technology, 2016 | 12 | 2016 |
| Comparative analysis of variable NT sram cells AK Dadoria, AS Yadav, CM Roy International Journal of Advanced Research in Computer Science and Software …, 2013 | 10 | 2013 |
| A new Approach for Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS circuit for VLSI Application H Malviya, S Nayar, CM Roy IEEE Int. Solid State Circuits Conf.(ISSCC) Dig. Tech 3, 11-16, 2013 | 8 | 2013 |
| Highly stable subthreshold single-ended 7T SRAM cell N Anand, C Roy, A Islam 2014 2nd international conference on emerging technology trends in …, 2014 | 5 | 2014 |
| A new approach for leakage power reduction techniques in deep submicron technologies in CMOS circuit for VLSI applications SN HinaMalviya, CM Roy Int J Adv Res Comput Sci Softw Eng 3 (5), 2013 | 5 | 2013 |
| Modeling of MTJ and its validation using nanoscale MRAM bitcell C Roy, A Bhattacharya, A Islam Journal of Engineering Science and Technology 12 (6), 1525-1540, 2017 | 2 | 2017 |
| Design of 10T SRAM cell using column-line assist and DTMOS techniques C Roy, A Islam Indian Journal of Science and Technology, 2016 | 1 | 2016 |
| A Linear Matric Inequality based Multi-loop PI control Design for Coupled Multivariable Liquid Level System SR Mahapatro, C Roy, R Patel, S Das | | 2024 |
| Theoretical optimization and design of graphene-based multiple-band terahertz absorbers for sensing applications SK Patel, R Kumar, AK Soni, C Tamrakar, C Roy Microsystem Technologies, 1-13, 2024 | | 2024 |
| Power Aware 10T Static Random-Access Memory Design M Rahul, V Vaishnavi, K Vyshnavi, C Roy 2023 2nd International Conference on Vision Towards Emerging Trends in …, 2023 | | 2023 |
| Design of High Noise Tolerant Single-Bit Line 8T SRAM Cell I Basha, P Hemanth, A Naidu, C Roy 2023 International Conference on Advances in Electronics, Communication …, 2023 | | 2023 |
| DESIGN OF NOISE TOLERANCE 9T SRAM CELL C Roy, JA Naveen, NK Reddy ICTACT Journal on Microelectronics, 1345-1349, 2022 | | 2022 |
| A Highly-Stable Read-Decoupled 6T-SRAM Cell at 16-nm Technology N Anand, A Sinha, C Roy, A Islam | | |
| HIGH STABLE AND POWER EFFICIENT 8 TRANSISTOR (8T) STATIC RANDOM ACCESS (SRAM) CACHE MEMORY C Roy | | |
Dr. Aminul IslamAssociate Professor, Birla Institute of Technology (Deemed to be University), Mesra, Ranchi, IndiaVerified email at ieee.org
