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Sharad Sinha
Sharad Sinha
Indian Institute of Technology (IIT), Goa
Verified email at iitgoa.ac.in - Homepage
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Cited by
Cited by
Year
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 430-437, 2017
1352017
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
J Zhao, T Liang, S Sinha, W Zhang
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
542019
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA
J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
532019
Low-Power FPGA Design Using Memoization-Based Approximate Computing
S Sinha, W Zhang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016
402016
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Z Lin, J Zhao, S Sinha, W Zhang
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 574-580, 2020
252020
Paas: A system level simulator for heterogeneous computing architectures
T Liang, L Feng, S Sinha, W Zhang
2017 27th International Conference on Field Programmable Logic and …, 2017
232017
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
J Zhao, T Liang, L Feng, W Ding, S Sinha, W Zhang, S Shen
2020 30th International Conference on Field-Programmable Logic and …, 2020
192020
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Z Lin, S Sinha, W Zhang
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
162019
Parallelizing Hardware Tasks on Multi-Context FPGA with Efficient Placement and Scheduling Algorithms
H Liang, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
162018
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
T Liang, J Zhao, L Feng, S Sinha, W Zhang
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019
152019
Heterosim: A heterogeneous cpu-fpga simulator
L Feng, H Liang, S Sinha, W Zhang
IEEE Computer Architecture Letters 16 (1), 38-41, 2017
132017
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
T Liang, J Zhao, L Feng, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
122018
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+ Evict
Z Kou, W He, S Sinha, W Zhang
2021 58th ACM/IEEE Design Automation Conference (DAC), 979-984, 2021
112021
Optimization of Convolutional Neural Networks on Resource Constrained Devices
A Sateesan, S Sinha, S KG
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019
112019
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
112018
Understanding industrial espionage for greater technological and economic security
S Sinha
IEEE Potentials 31 (3), 37-41, 2012
112012
Extended compatibility path based hardware binding algorithm for area-time efficient designs
U Dhawan, S Sinha, SK Lam, T Srikanthan
2nd Asia Symposium on Quality Electronic Design (ASQED), 151-156, 2010
112010
FinTech: The New Frontier
S Sinha
IEEE Potentials 36 (6), 6-7, 2017
102017
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
T Liang, G Chen, J Zhao, S Sinha, W Zhang
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
92021
A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs
A Sateesan, S Sinha, S KG, AP Vinod
Neural Processing Letters 53 (3), 2331-2377, 2021
92021
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