| Design of 4-Bit Reversible Shift Registers AV Ananthalakshmi, GF Sudha Wseas Transactions on Circuits and Systems, 2013 | 21 | 2013 |
| A Novel Power Efficient 0.64 - GFlops Fused 32-Bit Reversible Floating Point Arithmetic Unit Architecture for Digital Signal Processing Applications GFS AV Ananthalakshmi Microprocessors and Microsystems, Elsevier, 2017 | 19 | 2017 |
| Design of a reversible floating-point square root using modified non-restoring algorithm AV AnanthaLakshmi, GF Sudha Microprocessors and Microsystems 50, 39-53, 2017 | 16 | 2017 |
| VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes AV Ananthalakshmi, P Rajagopalan International Journal of Information Technology 11, 829-840, 2019 | 14 | 2019 |
| Design of a reversible single precision floating point subtractor AV Anantha Lakshmi, GF Sudha SpringerPlus 3, 1-20, 2014 | 13 | 2014 |
| Design of an Efficient Reversible Single Precision Floating Point Multiplier GFS A.V.AnanthaLakshmi Journal of Bioinformatics and Intelligent Control 4 (1), 21-30, 2015 | 10* | 2015 |
| Design of an efficent reversible single precision floating point adder AV AnanthaLakshmi, GF Sudha International Journal of Computational Intelligence Studies 4 (1), pp. 2 - 30, 2015 | 9 | 2015 |
| Design of a novel reversible full adder and reversible full subtractor AV AnanthaLakshmi, GF Sudha Advances in Computing and Information Technology: Proceedings of the Second …, 2013 | 9 | 2013 |
| Design and Implemetation of efficient reversible even parity checker and generator AVAL S.S. Gayathri International Conference on Science, Engineering and Management Research …, 2014 | 7 | 2014 |
| Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method A Anjana, AV Ananthalakshmi 2016 2nd International Conference on Advances in Electrical, Electronics …, 2016 | 4 | 2016 |
| Transistor Representation of a Low Power Reversible 32-Bit Comparator AV AnanthaLakshmi, GF Sudha International Conference on ICACNI 2013, 2013 | 4 | 2013 |
| AREA AND SPEED EFFICIENT REVERSIBLE FUSED RADIX-2 FFT BUTTERFLY UNIT USING 4:3 COMPRESSOR AV AnanthaLakshmi, GF Sudha International Journal on Recent Trends in Engineering and Technology 10 (1 …, 2014 | 3 | 2014 |
| An Efficient Implementation of a Reversible Single Precision Floating Point Multiplier Using 4:3 Compressor AV AnanthaLakshmi, GF Sudha International Conference on AIM 2013, 229-232, 2013 | 3 | 2013 |
| Design and Analysis of Pruned Approximate Majority Logic Based Adder PD Parameswari, AV Ananthalakshmi 2023 Second International Conference on Advances in Computational …, 2023 | 2 | 2023 |
| An energy efficient Montgomery modular multiplier for security systems using reversible gates MMA Kadar, AV Ananthalakshmi 2015 International Conference on Communications and Signal Processing (ICCSP …, 2015 | 2 | 2015 |
| An efficient carry save multiplier for signal processing applications D Parameswari, AV Ananthalakshmi International Journal of Computing and Digital Systems 13 (1), 1-1, 2023 | 1 | 2023 |
| Effective Diagnosis of Diabetes Mellitus Using Neural Networks and its Hardware Implementation on FPGA AV Ananthalakshmi International Journal of Computer Science and Information Security 15 (1), 519, 2017 | 1 | 2017 |
| Machine Learning-Driven Paradigms in VLSI Design: Exploring the Synergy with Pruning for Optimal Circuit Efficiency PD Parameswari, AV Ananthalakshmi 2024 Parul International Conference on Engineering and Technology (PICET), 1-4, 2024 | | 2024 |
| Review of Posit Arithmetic and its use in Deep Learning AV Ananthalakshmi International Journal of Research and Analytical Reviews 10 (2), 2023 | | 2023 |
| Intelligent Real time traffic management system TGAVA F. Frankline Marie International Journal of Computer Science and Information Security 18 (6), 2020 | | 2020 |
Gnanou Florence SudhaElectronics & Comunication Engineering, Puducherry Technological UniversityVerified email at ptuniv.edu.in
