| A Robust Method for Face Recognition and Face Emotion Detection System using Support Vector Machines KM Rajesh, M Naveenkumar International Conference on Electrical, Electronics, Communication, Computer …, 2016 | 55 | 2016 |
| An Adaptive-Profile Modified Active Shape Model for Automatic Landmark Annotation using OpenCV M Naveenkumar, KM Rajesh International Journal of Engineering Research in Electronic and …, 2016 | 4 | 2016 |
| Coherent receivers for fiber optic communications ES Shivaleela, M Naveenkumar ISSS Journal of Micro and Smart Systems ,Springer, 207–216, 2022 | 1 | 2022 |
| Design and Verification of Wishbone Compliant Serial Peripheral Interface NM Purushotham S International Journal of Engineering Research & Technology (IJERT), NCESC …, 2018 | 1 | 2018 |
| Experimental Demonstration of Optical PAM-4 Generation for Short-Reach Optical Communications M Naveenkumar, VSCS Vaddadi, ES Shivaleela 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), 547-551, 2022 | | 2022 |
| Evaluation of the Descriptive Type Answers using Neural Network Based OCR and Self-Organizing Map NM Suma D K INTERNATIONAL JOURNAL OF RESEARCH IN ELECTRONICS AND COMPUTER ENGINEERING …, 2019 | | 2019 |
| TRANSFER OF MEDICAL IMAGES IN DICOM STANDARDS USING WADO AND WADA SERVICES. NKM Lavanya K INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS (IJCRT) 6 (2), 211-214, 2018 | | 2018 |
| 4 Bit Flash ADC Configuration utilizing TMCC and NOR ROM Encoder using 180nm CMOS Technology DC KruthikChand, M Naveenkumar International Conference on “Signal, Image Processing, Communication and …, 2017 | | 2017 |
| FPGA Execution of USB Transceiver Macrocell Interface with USB 2.0 particulars C VinodKumar, M Naveenkumar International Conference on “Signal, Image Processing, Communication and …, 2017 | | 2017 |
| Design and Implementation of AES-128 on FPGA and preliminary Side Channel Analysis A Ahamed, M Naveenkumar International Conference on Current Innovations in Engineering and …, 2015 | | 2015 |
| BER Performance Analysis of Bit Flipping Algorithms used for Decoding LDPC Codes G Pavithra, M Naveenkumar International Journal of Engineering Research & Technology 4 (5), 10.17577 …, 2015 | | 2015 |
| Unified Model for Real World Recognition System using HOG features RS Sandhya, M Naveenkumar International Conference on Networks, Information and Communications 2014 …, 2014 | | 2014 |
| Image Encryption and Compression using Different Scalable Techniques R Devaraj, M Naveenkumar National Conference on Emerging Trends in Communication and Biomedical …, 2014 | | 2014 |
| Modified Digital Image Watermark Embedding Technique using combine DWT-DCT AM Nagarjun, M Naveenkumar National Conference on Advanced Research in Electronics & Communication …, 2014 | | 2014 |
| Low Power Asynchronous Binary-Search ADC Using Clock Gating Technique NP Suchithra, M Naveenkumar, JC Nidagundi International Conference ICFOCS 2011, 2011 | | 2011 |
| Design and Simulation of Low Power and High Speed Comparator using VLSI Technology NP Suchithra, M Naveenkumar, N Jayashree C. National Conference NCSCV’11, 2011 | | 2011 |
| Design and Verification of Low Power and High Speed Comparator using VLSI Technology NP Suchithra, M Naveenkumar, N Jayashree C. Conference on Evolutionary Trends in Information Technology, 2011 | | 2011 |
| Implementation of Multiplication using Redundant Radix-4 Number System on FPGA M Naveenkumar, M Sunil ,S. National Conference N4C-11, 2011 | | 2011 |
| Implementation of Reconfigurable Redundant Radix-4 Arithmetic Co-Processor M Naveenkumar, SS Mathad Programmable Device Circuits and Systems 3 (8), 428-435, 2011 | | 2011 |
| Low Power and High Speed Clock Triggered Comparator Using 0.18 μm Technology M Naveenkumar, NP Suchithra, JC Nidagundi, SS Mathad Programmable Device Circuits and Systems 3 (8), 436-440, 2011 | | 2011 |
E S ShivaleelaIndian Institute of ScienceVerified email at ece.iisc.ernet.in
