Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Y Huang, SM Reddy, WT Cheng, P Reuter, N Mukherjee, CC Tsai, ... Proceedings. International Test Conference, 74-82, 2002 | 213 | 2002 |
Resource allocation and test scheduling for concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... Proceedings 10th Asian Test Symposium, 265-270, 2001 | 185 | 2001 |
Bit selection algorithm suitable for high-volume production of SRAM-PUF K Xiao, MT Rahman, D Forte, Y Huang, M Su, M Tehranipoor 2014 IEEE international symposium on hardware-oriented security and trust …, 2014 | 156 | 2014 |
SOC test scheduling using simulated annealing W Zou, SM Reddy, I Pomeranz, Y Huang Proceedings. 21st VLSI Test Symposium, 2003., 325-330, 2003 | 144 | 2003 |
Survey of scan chain diagnosis Y Huang, R Guo, WT Cheng, JCM Li IEEE Design & Test of Computers 25 (3), 240-248, 2008 | 97 | 2008 |
Statistical diagnosis for intermittent scan chain hold-time fault Y Huang, WT Cheng, SM Reddy, CJ Hsieh, YT Hung ITC, 319-328, 2003 | 86 | 2003 |
Compactor independent direct diagnosis of test hardware Y Huang, WT Cheng, J Rajski US Patent 7,729,884, 2010 | 69 | 2010 |
Compactor independent direct diagnosis WT Cheng, KH Tsai, Y Huang, N Tamarapalli, J Rajski 13th Asian Test Symposium, 204-209, 2004 | 66 | 2004 |
Effects of embedded decompression and compaction architectures on side-channel attack resistance C Liu, Y Huang 25th IEEE VLSI Test Symposium (VTS'07), 461-468, 2007 | 61 | 2007 |
Compressed pattern diagnosis for scan chain failures Y Huang, WT Cheng, J Rajski IEEE International Conference on Test, 2005., 8 pp.-751, 2005 | 60 | 2005 |
Compactor independent fault diagnosis WT Cheng, KH Tsai, Y Huang, N Tamarapalli, J Rajski US Patent 7,239,978, 2007 | 52* | 2007 |
Diagnosis with limited failure information Y Huang, WT Cheng, N Tamarapalli, J Rajski, R Klingenberg, W Hsu, ... 2006 IEEE International Test Conference, 1-10, 2006 | 44 | 2006 |
Scan chain diagnosis by adaptive signal profiling with manufacturing ATPG patterns Y Huang, WT Cheng, R Guo, TP Tai, FM Kuo, YS Chen 2009 Asian Test Symposium, 35-40, 2009 | 42 | 2009 |
Improved volume diagnosis throughput using dynamic design partitioning X Fan, H Tang, Y Huang, WT Cheng, SM Reddy, B Benware 2012 IEEE International Test Conference, 1-10, 2012 | 41 | 2012 |
Fault dictionary based scan chain failure diagnosis R Guo, Y Huang, WT Cheng 16th Asian Test Symposium (ATS 2007), 45-52, 2007 | 40* | 2007 |
Dynamic learning based scan chain diagnosis Y Huang 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 39 | 2007 |
On concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 37-50, 2002 | 39 | 2002 |
Detecting causality from time series in a machine learning framework Y Huang, Z Fu, CLE Franzke Chaos: An Interdisciplinary Journal of Nonlinear Science 30 (6), 2020 | 36 | 2020 |
Scan shift power reduction by freezing power sensitive scan cells X Lin, Y Huang Journal of Electronic Testing 24, 327-334, 2008 | 36 | 2008 |
Intermittent scan chain fault diagnosis based on signal probability analysis Y Huang, WT Cheng, CJ Hsieh, HY Tseng, A Huang, YT Hung Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 36 | 2004 |