| On minimization of peak power for scan circuit during test JT Tudu, E Larsson, V Singh, VD Agrawal 2009 14th IEEE European Test Symposium, 25-30, 2009 | 41 | 2009 |
| A high performance scan flip-flop design for serial and mixed mode scan test S Ahlawat, J Tudu, A Matrosova, V Singh IEEE Transactions on Device and Materials Reliability 18 (2), 321-331, 2018 | 20 | 2018 |
| On securing scan design through test vector encryption D Vaghani, S Ahlawat, J Tudu, M Fujita, V Singh 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 18 | 2018 |
| On securing scan design from scan-based side-channel attacks S Ahlawat, D Vaghani, J Tudu, V Singh 2017 IEEE 26th Asian Test Symposium (ATS), 58-63, 2017 | 12 | 2017 |
| A new scan flip flop design to eliminate performance penalty of scan S Ahlawat, J Tudu, A Matrosova, V Singh 2015 IEEE 24th Asian Test Symposium (ATS), 25-30, 2015 | 10 | 2015 |
| Preventing scan attack through test response encryption S Ahlawat, J Tudu, MS Gaur, M Fujita, V Singh 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019 | 9 | 2019 |
| LUT-based circuit approximation with targeted error guarantees GU Vinod, VS Vineesh, JT Tudu, M Fujita, V Singh 2020 IEEE 29th Asian Test Symposium (ATS), 1-6, 2020 | 7 | 2020 |
| Graph theoretic approach for scan cell reordering to minimize peak shift power JT Tudu, E Larsson, V Singh, H Fujiwara Proceedings of the 20th symposium on Great lakes symposium on VLSI, 73-78, 2010 | 7 | 2010 |
| A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture B Kumar, B Nehru, B Pandey, V Singh, J Tudu 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | 6 | 2016 |
| On minimization of test power through modified scan flip-flop S Ahlawat, JT Tudu 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 6 | 2016 |
| Jscan: A joint-scan dft architecture to minimize test time, pattern volume, and power J Tudu 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 6 | 2016 |
| Securing scan through plain-text restriction S Ahlawat, K Ahirwar, J Tudu, M Fujita, V Singh 2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019 | 4 | 2019 |
| A cost effective technique for diagnosis of scan chain faults S Ahlawat, D Vaghani, J Tudu, A Suhag International Symposium on VLSI Design and Test, 191-204, 2017 | 4 | 2017 |
| On determination of instantaneous peak and cycle peak switching using ILP R Gulve, N Hage, J Tudu 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 4 | 2016 |
| Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach JT Tudu, E Larsson, V Singh, H Fujiwara 2010 15th IEEE European Test Symposium, 259-259, 2010 | 4 | 2010 |
| Generation of minimal leakage input vectors with constrained NBTI degradation P Subramanyan, RR Jangir, JT Tudu, E Larsson, V Singh | 4 | 2009 |
| Scan cells reordering to minimize peak power during scan testing of SOC JT Tudu, E Larsson, V Singh, H Fujiwara IEEE WRTLT, 2009 | 3 | 2009 |
| On protecting IJTAG from data sniffing and alteration attacks A Riaz, G Kumar, J Tudu, S Ahlawat 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 146-151, 2022 | 2 | 2022 |
| ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits JT Tudu, D Malani, V Singh Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 2 | 2012 |
| On selection of state variables for delay test of identical functional units A Kajala, G Sinsinwar, RR Choudhary, J Tudu, V Singh 2010 East-West Design & Test Symposium (EWDTS), 200-203, 2010 | 2 | 2010 |
Virendra SinghAssociate Professor of Electrical Engineering, Indian Institute of Technology BombayVerified email at ee.iitb.ac.in
