An efficient MRTD model for the analysis of crosstalk in CMOS-driven coupled Cu interconnects S Rebelli, BR Nistala Radioengineering 27 (2), 532-540, 2018 | 12 | 2018 |
Design and performance optimization of junctionless bottom spacer FinFET for digital/analog/RF applications at sub-5nm technology node S Valasa, KV Ramakrishna, N Vadthiya, S Bhukya, NB Rao, ... ECS Journal of Solid State Science and Technology 12 (1), 013004, 2023 | 11 | 2023 |
The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges SR Suddapalli, BR Nistala Journal of Computational Electronics 20 (1), 492-502, 2021 | 11 | 2021 |
A center-potential-based threshold voltage model for a graded-channel dual-material double-gate strained-Si MOSFET with interface charges SR Suddapalli, BR Nistala Journal of Computational Electronics 18 (4), 1173-1181, 2019 | 11 | 2019 |
3D inductor for RF applications NB Rao, AN Chandorkar International Journal of Microwave and Optical Technology 3 (4), 445-450, 2008 | 11 | 2008 |
Miniature on-chip band pass filter for RF applications BN Deevi, NB Rao Microsystem Technologies 23, 633-638, 2017 | 10 | 2017 |
Variable gate oxide thickness MOSFET: A device level solution for sub-threshold leakage current reduction KK Kumar, NB Rao 2012 International Conference on Devices, Circuits and Systems (ICDCS), 495-498, 2012 | 9 | 2012 |
Circuit level analysis of a dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET at nanoscale regime PK Mudidhe, BR Nistala ECS Journal of Solid State Science and Technology 12 (6), 063002, 2023 | 8 | 2023 |
A multiresolution time domain (MRTD) method for crosstalk noise modeling of CMOS-gate-driven coupled MWCNT interconnects S Rebelli, BR Nistala IEEE Transactions on Electromagnetic Compatibility 62 (2), 521-531, 2019 | 8 | 2019 |
Fractal spiral capacitor for wireless applications P Akhendra Kumar, N Bheema Rao Electronics Letters 52 (6), 481-483, 2016 | 8 | 2016 |
Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short-channel effects PK Mudidhe, BR Nistala Journal of Computational Electronics 22 (1), 199-208, 2023 | 7 | 2023 |
Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance SR Suddapalli, BR Nistala International journal of numerical modelling: Electronic networks, devices …, 2021 | 7 | 2021 |
Fractal series stacked inductor for radio frequency integrated circuit applications P Akhendra Kumar, N Bheema Rao Electronics Letters 53 (20), 1387-1388, 2017 | 7 | 2017 |
An efficient delay estimation model for high speed VLSI interconnects M Kavicharan, NS Murthy, NB Rao 2013 International Conference on Advances in Computing, Communications and …, 2013 | 7 | 2013 |
Analog/RF performance of triple material gate stack-graded channel double gate-junctionless strained-silicon MOSFET with fixed charges SS Rao, RDB Joseph, VD Chintala, GK Saramekala, D Srikar, NB Rao Silicon, 1-14, 2022 | 6 | 2022 |
High inductance fractal inductors for wireless applications AK Padavala, BR Nistala Turkish Journal of Electrical Engineering and Computer Sciences 25 (5), 3868 …, 2017 | 6 | 2017 |
Performance analysis of dual material graded channel cylindrical gate all around (DMGC CGAA) FET with source/drain underlap PK Mudidhe, BR Nistala 2022 IEEE International Symposium on Smart Electronic Systems (iSES), 302-306, 2022 | 5 | 2022 |
A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects S Rebelli, BR Nistala COMPEL-The international journal for computation and mathematics in …, 2018 | 5 | 2018 |
Microelectronics, Electromagnetics and Telecommunications SC Satapathy, NB Rao, SS Kumar, CD Raj, VM Rao, GVK Sarma Proceedings of ICMEET, 779, 2015 | 5 | 2015 |
C-based predictor for scoreboard in Universal Verification Methodology S Konale, NB Rao 2014 International Conference on Advances in Engineering & Technology …, 2014 | 5 | 2014 |