| Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage AS Khade, V Vyas, M Sutaone Integration 69, 242-250, 2019 | 23 | 2019 |
| Design and optimization of 16× 16 Bit multiplier using Vedic mathematics SN Gadakh, A Khade 2016 International Conference on Automatic Control and Dynamic Optimization …, 2016 | 19 | 2016 |
| FPGA implementation of high speed vedic multiplier SN Gadakh, AS Khade International Conference & Workshop on Electronics & Telecommunication …, 2016 | 16 | 2016 |
| Transconductance enhancement of a low voltage low power recycling folded cascode OTA using an asymmetrical current split input stage AS Khade, V Vyas, M Sutaone, S Musale Microelectronics Journal 91, 53-60, 2019 | 13 | 2019 |
| A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier AS Khade, S Musale, R Suryawanshi, V Vyas Analog Integrated Circuits and Signal Processing 107, 227-238, 2021 | 8 | 2021 |
| A technique to enhance the transconductance of micro-power improved recycling folded cascode operational transconductance amplifier with reasonable phase margin AS Khade, V Vyas, M Sutaone AEU-International Journal of Electronics and Communications 108, 148-157, 2019 | 5 | 2019 |
| A low power super class ab rfc ota suitable for biomedical applications VV Bhise, AS Khade, V Vyas 2019 10th International Conference on Computing, Communication and …, 2019 | 1 | 2019 |
| Operational Transconductance Amplifier Structured Highly Linear Analog Multiplier AS Khade, V Vyas Proceedings of the Third International Conference on Microelectronics …, 2019 | | 2019 |
| Communications (AEÜ) AS Khade, V Vyas, M Sutaone | | |
| Design and optimization of low power CMOS operational transconductance amplifier AS Khade Pune, 0 | | |
