| Non-additive noise reduction in medical images using bilateral filtering and modular neural networks M Kalaiyarasi, R Janaki, A Sampath, D Ganage, YD Chincholkar, ... Soft Computing, 1-10, 2023 | 2 | 2023 |
| Study on power minimization techniques in SAR ADC devices by using comparators circuits PD Sree, BJ Raj, B Srinivas Journal of Physics: Conference Series 1714 (1), 012043, 2021 | 1 | 2021 |
| Development of FFT Processor: A Succinct Study PB Varma, R Dheeraj, Abhitej, S Budaraju | | 2021 |
| Performance analysis of Fused Add-Multiply (FAM) architectures * Y. Leela Madhuri1 , Md. Nafeesa Begum2 , B. Srinivas3 ADALYA JOURNAL 9 (12), 47-53, 2020 | | 2020 |
| A NOVEL MULTIBIT ERROR PREDICTION AND 32 BIT ERROR COORRECTION IN MEMORIES USING DMC BS VENU KUMARI IJIRMET 3 (1), 2018 | | 2018 |
| Basys 2tm FPGA based robotic hand with 6 degrees of freedom VN Srinivas Budaraju International Conference on Electrical, Electronics and Commubication Engg …, 2017 | | 2017 |
| Implementation of MDC FFT/IFFT processor for MIMO-OFDM systems BS M.Gangadhar WJES 3 (6), 1-8, 2016 | | 2016 |
| An Optimized Fused Add-Multiply (FAM) Operator Chilukuri, Nageswara Rao, Budaraju Srinivas, Penumutchi Bujjibabu IJRSET 2 (5), 36-41, 2015 | | 2015 |
| background subtraction algorithmfor object recognition implementation on FPGA BS R.Rajasekhar International jounal of science, Engineering and Technology research 3 (46 …, 2014 | | 2014 |
| Design of DDR3 SDRAM controller for achieving high speed read operation GH S.Ch.Kantharao, B.Srinivas, U.Yedukondalu IJRSAT 1 (2), 013-016, 2013 | | 2013 |
Bujjibabu Penumutchi, M.Tech.,(Ph.D.)...Aditya Engineering College Surampalem, JNTUKVerified email at aec.edu.in
