| A Charge-Plasma-Based Dielectric-Modulated Junctionless TFET for Biosensor Label-Free Detection D Singh, S Pandey, K Nigam, D Sharma, DS Yadav, P Kondekar IEEE Transactions on Electron Devices 64 (1), 271-278, 2017 | 178 | 2017 |
| Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor M Verma, S Tirkey, S Yadav, D Sharma, DS Yadav IEEE transactions on electron devices 64 (9), 3841-3848, 2017 | 150 | 2017 |
| Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping S Ahish, D Sharma, YBN Kumar, MH Vasantha IEEE Transactions on Electron Devices 63 (1), 288-295, 2016 | 142 | 2016 |
| A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics BR Raad, S Tirkey, D Sharma, P Kondekar IEEE Transactions on Electron Devices 64 (4), 1830-1836, 2017 | 122 | 2017 |
| Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications PN Kondekar, K Nigam, S Pandey, D Sharma IEEE Transactions on Electron Devices 64 (2), 412-418, 2017 | 110 | 2017 |
| Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications DS PN Kondekar, K Nigam, S Pandey IEEE Transactions on Electron Devices 64 (02), 412-418, 1920 | 110* | 1920 |
| Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation BR Raad, D Sharma, P Kondekar, K Nigam, DS Yadav IEEE Transactions on Electron Devices 63 (10), 3950-3957, 2016 | 107 | 2016 |
| Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement BR Raad, K Nigam, D Sharma, PN Kondekar Superlattices and Microstructures 94, 138-146, 2016 | 91 | 2016 |
| Features based on analytic IMF for classifying motor imagery EEG signals in BCI applications S Taran, V Bajaj, D Sharma, S Siuly, A Sengur Measurement 116, 68-76, 2018 | 90 | 2018 |
| Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement B Raad, K Nigam, D Sharma, P Kondekar Electronics Letters 52 (9), 770-772, 2016 | 84 | 2016 |
| Analysis of a Novel Metal Implant Junctionless Tunnel FET for Better DC and Analog/RF Electrostatic Parameters S Tirkey, D Sharma, DS Yadav, S Yadav IEEE transactions on electron devices 64 (9), 3943-3950, 2017 | 73 | 2017 |
| An efficient method for analysis of EMG signals using improved empirical mode decomposition VK Mishra, V Bajaj, A Kumar, D Sharma, GK Singh AEU-International Journal of Electronics and Communications 72, 200-209, 2017 | 68 | 2017 |
| DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor K Nigam, P Kondekar, D Sharma Superlattices and Microstructures 92, 224-231, 2016 | 68 | 2016 |
| Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET S Gupta, K Nigam, S Pandey, D Sharma, PN Kondekar IEEE Transactions on Electron Devices 64 (11), 4731-4737, 2017 | 67 | 2017 |
| A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement K Nigam, S Pandey, PN Kondekar, D Sharma, PK Parte IEEE Transactions on Electron Devices 64 (6), 2751-2757, 2017 | 63 | 2017 |
| Approach for ambipolar behaviour suppression in tunnel FET by workfunction engineering K Nigam, D Sharma Micro & Nano Letters 11 (8), 460-464, 2016 | 59 | 2016 |
| A dielectrically modulated electrically doped tunnel FET for application of label free biosensor P Venkatesh, K Nigam, S Pandey, D Sharma, PN Kondekar Superlattices and Microstructures 109, 470-479, 2017 | 58 | 2017 |
| Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric P Venkatesh, K Nigam, S Pandey, D Sharma, PN Kondekar IEEE Transactions on Device and Materials Reliability 17 (1), 245-252, 2017 | 57 | 2017 |
| Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level J Patel, D Sharma, S Yadav, A Lemtur, P Suman Microelectronics Journal, 2019 | 56 | 2019 |
| Precise analytical model for short channel cylindrical gate (CylG) gate-all-around (GAA) MOSFET D Sharma, SK Vishvakarma Solid-State Electronics 86, 68-74, 2013 | 53 | 2013 |
Bhagwan Ram RaadPDPM Indian Institute of Information Technology, Design and Manufacturing JabalpurVerified email at iiitdmj.ac.in
