| Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter R Sakthivel, G Ragunath Journal of Ambient Intelligence and Humanized Computing 12, 5513-5524, 2021 | 9 | 2021 |
| Delay optimized binary to BCD converter for multi-operand parallel decimal adder G Ragunath, V Sugandh, R Sakthivel 2019 International conference on vision towards emerging trends in …, 2019 | 4 | 2019 |
| Low-Power and Area-Efficient Square –Root Carry Select Adders using Modified XOR Gate G Ragunath, R Sakthivel Indian Journal of Science and Technology, 2016 | 2 | 2016 |
| An Area Efficient 16-bit Logarithmic Multiplier MBK Chaitanya, YS Teja, KR Teja, G Ragunath 2019 International Conference on Vision Towards Emerging Trends in …, 2019 | | 2019 |
| Low Power Pre-Charge Free DCAM CVSRN Immadisetti, G Ragunath 2019 International Conference on Vision Towards Emerging Trends in …, 2019 | | 2019 |
