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Dr.D.Jayanthi
Dr.D.Jayanthi
Gokaraju Rangaraju Institute of Engineering and Technology Hyderabad
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Cited by
Year
Design and development of graphene FET biosensor for the detection of SARS-CoV-2
BV Krsihna, S Ahmadsaidulu, SST Teja, D Jayanthi, A Navaneetha, ...
Silicon, 1-9, 2022
352022
A modernistic way for KEY generation for highly secure data transfer in ASIC design flow
TR Patnala, D Jayanthi, S Majji, M Valleti, S Kothapalli, SR Karanam
2020 6th International conference on advanced computing and communication …, 2020
292020
Maximal length test pattern generation for the cryptography applications
TR Patnala, D Jayanthi, DS Shylu, K Kavitha, P Chowdary
meterialstoday proceedings 2, 2020
232020
Early heart disease prediction using ensemble learning techniques
KR Chowdary, P Bhargav, N Nikhil, K Varun, D Jayanthi
Journal of Physics: Conference Series 2325 (1), 012051, 2022
102022
A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process
DSS Sam, PS Paul, D Jayanthi
2021 7th International Conference on Advanced Computing and Communication …, 2021
82021
Key-based functional obfuscation of integrated circuits for a hardware security
RU Rani, D Jayanthi, NA Vignesh, K Kavitha
2019 2nd International Conference on Intelligent Computing, Instrumentation …, 2019
52019
High Speed Multioutput Circuits Using Adiabatic Logic
GR D.Jayanthi
International Conference Kings engineering College,Thanjavur(ICETETS-16)., 2016
52016
Malware Identification in Advanced Interconnects on SOC
G Sangeeth, D Jayanthi, R Krishna, P Ilanchezhian, DSS Sam
2022 International Virtual Conference on Power Engineering Computing and …, 2022
32022
Hardware Security for Digital Circuits from Hardware Trojans
J Hrushikesh, D Jayanthi, K Jamal
International Journal of Pure and Applied Mathematics 119 (17), 3169-3177, 2018
22018
Certain investigations on reduced power consumption in sequential circuits
D Jayanthi
Chennai, 2013
22013
The Design of High Performance Asynchronous Pipelines with Quasi Delay Insensitive
JD Rajaram.M
International Journal of Computer Applications 52 (16), 35-41, 2012
2*2012
Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process
DSS Sam, G Manoj, D Jayanthi, S Babafakruddin, EGV Shriashwinraja
2023 4th International Conference on Signal Processing and Communication …, 2023
12023
TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications
S Varma, CP Chowdari, D Jayanthi, AK Panigrahi, K Jamal
2022 13th International Conference on Computing Communication and Networking …, 2022
12022
Hardware Security for DSP Circuits Using Key-Based Time-Dependent Obfuscation
R Uma Rani, D Jayanthi, S Jayabalan, A Vignesh
Advances in Smart Grid Technology: Select Proceedings of PECCON 2019—Volume …, 2020
12020
Maximal length test pattern generation for the cryptography application
PT Radhika, D Jayanthi, DS Shylu, K Kavitha, CP Chowdary
Materials Today: Proceedings 33, 2701-2705, 2020
12020
A Quasi Delay Insensitive ReducedStack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits
JD Rajaram.M
Journal of Computer Science 8 (7), 1114-1122, 2012
12012
Design of 40‐nm Hetero‐Dielectric Tri‐Material Gate Tunnel FET Using Visual TCAD
Nasreen, G Sreeja, AM Reddy, D Jayanthi, R Krishna, K Kavitha
Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart …, 2024
2024
3D Design of Gate All‐Around Field Effect Transistor Using Visual TCAD
B Srujana, D Jayanthi, R Krishna, DS Shylusam
Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart …, 2024
2024
Design and Simulation of 10‐nm SOI TRI‐Gate FinFET Using TCAD
R Mohammed, D Jayanthi, H Munja, R Krishna, A Pulgam, ...
Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart …, 2024
2024
Trigate Junctionless Tunnel Field Effect Transistor
P Gudelli, D Jayanthi, D Illuri, R Krishna, R Pendoti, P Ilanchezhian
Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart …, 2024
2024
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