| Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2019 32nd international conference on VLSI Design and 2019 18th …, 2019 | 17 | 2019 |
| A novel fault-tolerant routing algorithm for mesh-of-tree based network-on-chips M Shah, M Upadhyay, PV Bhanu, J Soumya, LR Cenkeramaddi VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai …, 2019 | 3 | 2019 |
| Fault tolerant routing methodology for mesh-of-tree based network-on-chips using local reconfiguration M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2018 International Conference on High Performance Computing & Simulation …, 2018 | 3 | 2018 |
| Patternet: explore and exploit filter patterns for efficient deep neural networks B Khaleghi, U Mallappa, D Yaldiz, H Yang, M Shah, J Kang, T Rosing Proceedings of the 59th ACM/IEEE Design Automation Conference, 223-228, 2022 | 2 | 2022 |
| A novel fault-tolerant routing technique for mesh-of-tree based network-on-chip design M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkarmaddi, H Idsøe TENCON 2018-2018 IEEE Region 10 Conference, 2378-2383, 2018 | 1 | 2018 |
Soumya JAssociate Professor at BITS Pilani, Hyderabad CampusVerified email at hyderabad.bits-pilani.ac.in
