| Analysis of 6T SRAM Cell in Different Technologies S Rath, SK Panda | 15 | 2017 |
| VLSI Implementation of Vedic Multiplier Using Urdhva–Tiryakbhyam Sutra in VHDL Environment: A Novelty SK Panda, R Das, SKS Raheman, TR Sahoo IOSR Journal of VLSI and Signal Processing (IOSR-JVSP),UGC approved journal …, 2015 | 13 | 2015 |
| A novel vedic divider architecture with reduced delay for VLSI applications SK Panda, A Sahu International Journal of Computer Applications,Indexed in NASA ADS (Harvard …, 2015 | 10 | 2015 |
| FPGA-VHDL implementation of Pipelined Square root Circuit for VLSI Signal Processing Applications SK Panda, A Jena International journal of Computer applications 142 (5), 20-24, 2016 | 7 | 2016 |
| Developing High-Performance AVM Based VLSI Computing Systems: A Study SK Panda, DC Panda Progress in Computing, Analytics and Networking,Springer Publisher, 315-323, 2018 | 6 | 2018 |
| VHDL implementation of a Novel Low power squaring circuit using YTVY algorithm of Vedic Mathematics PK Mohapatra, SK Panda, S Dalal, S Pradhan International Journal of Emerging Trends in Science and Technology 2 (3 …, 2015 | 5 | 2015 |
| Revision of Various Square-Root algorithms for efficient VLSI Signal processing applications A Jena, SK Panda IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), 0 | 5* | |
| An optimized procedure for investigation of problem in marketing strategy: a review SK Panda, A Padhy, J Pani, SR Rout, BN Panda Int. J. Extensive Res 3, 72-78, 2015 | 4 | 2015 |
| HDL Implementation and Performance Comparison of an Optimized High Speed Multiplier A Sahu, SK Panda IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 5 (2), 10-19, 0 | 4* | |
| FPGA implementation of Angle Generator for CORDIC Based High pass FIR Filter Design N Das, S Jena, SK Panda IOSR Journal of Electronics and Communication Engineering, 1-11, 2016 | 3 | 2016 |
| An Efficient Segmentation Technique for Machine Printed Devanagiri Script: Both Line &Word Segmentation SK Panda, SS Pani, BN Panda | 2* | |
| Industry 4.0: A Road Map to Custom Register Transfer Level Design SK Panda, K Achyut, SK Kulkarni Advances in Industry 4.0: Concepts and Applications 5, 21, 2022 | 1 | 2022 |
| An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System—Understanding Complexity SK Panda, K Achyut, SK Kulkarni, AA Raut, A Nayak Artificial Intelligence Applications and Reconfigurable Architectures, 35-62, 2023 | | 2023 |
| An intelligent verification management approach for efficient VLSI computing system SK Siba Kumar Panda, Konasagar Achyut IET, 2022 | | 2022 |
| Design and Implementation of a Factorial Circuit for Binary Numbers: An AVM-Based VLSI Computing Approach SK Panda, A Sahoo, DC Panda Advanced Computing and Intelligent Engineering, 73-82, 2020 | | 2020 |
| N-bit Pipelined CSM Based Square Root Circuit for Binary Numbers SK Panda, A Jena, DC Panda Progress in Advanced Computing and Intelligent Engineering, Springer …, 2018 | | 2018 |
| Design of Low Power Transversal FIR Filter For VLSI Signal Processing Applications SS Pattnaik, R Das, SK Panda International Journal of Emerging Trends in Science and Technology 2 (04), 2015 | | 2015 |
| Design and Simulation of Convolution Using Booth Encoded Wallace Tree Multiplier JP Mohanty, R Das, SK Panda | | |
Swarna Prabha Jena , Asst. Prof.Centurion University of Technology & ManagementVerified email at cutm.ac.in
