| Role of semiconducting carbon nanotubes in crosstalk reduction of CNT interconnects PU Sathyakam, A Karthikeyan, PS Mallick IEEE transactions on nanotechnology 12 (5), 662-664, 2013 | 31 | 2013 |
| Optimization techniques for CNT based VLSI interconnects—a review A Karthikeyan, PS Mallick Journal of Circuits, Systems and Computers 26 (03), 1730002, 2017 | 22 | 2017 |
| Transmission gate as buffer for carbon-nanotube-based VLSI interconnects A Karthikeyan, PS Mallick IETE Journal of research 64 (2), 296-305, 2018 | 12 | 2018 |
| Reduction of crosstalk in mixed CNT bundle interconnects for high frequency 3D ICs and SoCs PU Sathyakam, A Karthikeyan, JK Rajesh, PS Mallick 2014 International Conference on Advances in Electrical Engineering (ICAEE), 1-3, 2014 | 11 | 2014 |
| Body-biased subthreshold bootstrapped CMOS driver A Karthikeyan, PS Mallick Journal of Circuits, Systems and Computers 28 (03), 1950051, 2019 | 7 | 2019 |
| High-speed and low-power repeater for VLSI interconnects A Karthikeyan, PS Mallick Journal of Semiconductors 38 (10), 105006, 2017 | 7 | 2017 |
| Performance comparison of AgTiO2 and CNT based latent heat materials on a solar pond N Poyyamozhi, A Karthikeyan Materials Today: Proceedings 47, 4548-4551, 2021 | 5 | 2021 |
| A Leakage Reduction Charge Pump based Domino Logic for Low Power VLSI Circuits A Karthikeyan, S Balaji, R Santhakumar, S Rajalakshmi, P Jayakrishnan International Journal of Intelligent Systems and Applications in Engineering …, 2022 | 2 | 2022 |
| A PSO based optimal repeater insertion technique for carbon nanotube interconnects P Uma Sathyakam, S Raj, A Karthikeyan, PS Mallick International Journal of Electronics Letters 10 (3), 344-353, 2022 | 2 | 2022 |
| Smart Hydroponics System for Soilless Farming Based on Internet of Things GV Danush Ranganath, R Hari Sri Rameasvar, A Karthikeyan Smart Technologies in Data Science and Communication: Proceedings of SMART …, 2023 | 1 | 2023 |
| Analysis of triangular CNT bundle interconnects for current mode signalling PU Sathyakam, S Das, A Karthikeyan 2019 Innovations in Power and Advanced Computing Technologies (i-PACT) 1, 1-4, 2019 | 1 | 2019 |
| High Performance Buffer with Body Biasing Technique A Karthikeyan, PS Mallick International Conference on Automation, Signal Processing, Instrumentation …, 2020 | | 2020 |
| Mixed CNT bundles as VLSI interconnects | | |
| Dual mode logic buffers for VLSI interconnects A Ilakkiya, A Karthikeyan, PU Sathyakam | | |
| Single Walled Carbon Nanotube Interconnects For Future Integrated Circuits P Bhardwaj, P Singh, PU Sathyakam, A Karthikeyan | | |
