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KIRAN BAILEY
KIRAN BAILEY
Assistant Professor of Electronics and communication, BMS College of Engineering
Verified email at bmsce.ac.in
Title
Cited by
Cited by
Year
3D device modeling and assessment of triple gate SOI FinFET for LSTP applications
K Bailey, KS Gurumurthy
International Journal of Computer Theory and Engineering 4 (5), 831, 2012
72012
Performance of 14nm SOI FinFET with ZrO2 dielectric: A Comparative Study
KB OushpaK, S Sunkara
Int. Journal of Engineering Research and General Science 3, 299-305, 2015
52015
Impact of device parameters of triple gate soi-finfet on the performance of cmos inverter at 22nm
A Prathima, K Bailey, KS Gurumurthy
International Journal of VLSI Design & Communication Systems 3 (5), 79, 2012
32012
Design Space Exploration of 14nm Gate All around MOSFET
R Alas, K Bailey
2015 Fifth International Conference on Advances in Computing and …, 2015
22015
Low power semiconductor devices at 65nm technology node
K Bailey, KS Gurumurthy
International Journal of Circuits, Systems and Signal Processing 4 (2), 2010
22010
Process Variability Analysis in 14-nm SOI FinFET Inverters‖
N Shanbhag, K Bailey, KS Gurumurthy
International Journal of Science, Engineering and Technology Research …, 2014
12014
Impact of Fin Dimensions and Gate DielectricThickness on the Static Power Dissipation of 6T-FinFET SRAM Cell
K Bailey, KS Gurumurthy
2013
Modeling and performance evaluation of UTB SGOI devices scalable to 22 nm technology node
K Bailey, KS Gurumurthy
WSEAS Transactions on Circuits and Systems 9 (10), 607-616, 2010
2010
Analysis and modeling of high performance and low power UTB SGOI devices scalable to sub 30 nm
K Bailey, KS Gurumurthy
International Conference on Circuits, Systems and Signals-Proceedings, 120-123, 2010
2010
65 nm CMOS devices for Low Power Applications
K Bailey, KS Gurumurthy
Proceedings of the 12th international conference on Networking, VLSI and …, 2010
2010
DESIGN AND IMPLEMENTATION OF SS-ADC COMPONENT USING FINFET TECHNOLOGY
MS Manur, K Bailey
Optimization of Gate Leakage for 22nm MOSFETs through Alternate High-k Materials using T-CAD simulations
BJ SOMAYAJI, K BAILEY
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