Smruti R. Sarangi
Smruti R. Sarangi
Computer Science, IIT Delhi
Verified email at - Homepage
Cited by
Cited by
Internet of things: architectures, protocols, and applications
P Sethi, SR Sarangi
Journal of electrical and computer engineering 2017 (1), 9324035, 2017
SESC simulator, January 2005
J Renau, B Fraguela, J Tuck, W Liu, M Prvulovic, L Ceze, S Sarangi, ...
VARIUS: A model of process variation and resulting timing errors for microarchitects
SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas
IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008
ReCycle: Pipeline adaptation to tolerate process variation
A Tiwari, SR Sarangi, J Torrellas
ACM SIGARCH Computer Architecture News 35 (2), 323-334, 2007
Virtual base station pool: towards a wireless network cloud for radio access networks
ZB Zhu, P Gupta, Q Wang, S Kalyanaraman, Y Lin, H Franke, S Sarangi
Proceedings of the 8th ACM international conference on computing frontiers, 1-10, 2011
EVAL: Utilizing processors with variation-induced timing errors
S Sarangi, B Greskamp, A Tiwari, J Torrellas
2008 41st IEEE/ACM International Symposium on Microarchitecture, 423-434, 2008
Accelerating CNN inference on ASICs: A survey
D Moolchandani, A Kumar, SR Sarangi
Journal of Systems Architecture 113, 101887, 2021
Cadre: Cycle-accurate deterministic replay for hardware debugging
SR Sarangi, B Greskamp, J Torrellas
International Conference on Dependable Systems and Networks (DSN'06), 301-312, 2006
Phoenix: Detecting and recovering from permanent processor design bugs with programmable hardware
SR Sarangi, A Tiwari, J Torrellas
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
DUST: a generalized notion of similarity between uncertain time series
SR Sarangi, K Murthy
Proceedings of the 16th ACM SIGKDD international conference on Knowledge …, 2010
Patching processor design errors with programmable hardware
S Sarangi, S Narayanasamy, B Carneal, A Tiwari, B Calder, J Torrellas
IEEE micro 27 (1), 12-25, 2007
Tejas: A java based versatile micro-architectural simulator
SR Sarangi, R Kalayappan, P Kallurkar, S Goel, E Peter
2015 25th International Workshop on Power and Timing Modeling, Optimization …, 2015
Thread-level speculation on a CMP can be energy efficient
J Renau, K Strauss, L Ceze, W Liu, S Sarangi, J Tuck, J Torrellas
Proceedings of the 19th annual international conference on Supercomputing …, 2005
Reslice: Selective re-execution of long-retired misspeculated instructions using forward slicing
SR Sarangi, W Liu, J Torrellas, Y Zhou
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005
A survey of on-chip optical interconnects
J Bashir, E Peter, SR Sarangi
ACM Computing Surveys (CSUR) 51 (6), 1-34, 2019
Optimizing workflow engines
D Saha, SR Sarangi
US Patent 8,510,751, 2013
A reference architecture for smart and software-defined buildings
M Mazzara, I Afanasyev, SR Sarangi, S Distefano, V Kumar, M Ahmad
2019 IEEE International Conference on Smart Computing (SMARTCOMP), 167-172, 2019
Active microring based tunable optical power splitters
E Peter, A Thomas, A Dhawan, SR Sarangi
Optics Communications 359, 311-315, 2016
Energy-efficient thread-level speculation
J Renau, K Strauss, L Ceze, W Liu, SR Sarangi, J Tuck, J Torrellas
IEEE Micro 26 (1), 80-91, 2006
GpuTejas: A parallel simulator for GPU architectures
G Malhotra, S Goel, SR Sarangi
2014 21st International Conference on High Performance Computing (HiPC), 1-10, 2014
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