| 0.84 ps resolution clock skew measurement via subsampling B Amrutur, PK Das, R Vasudevamurthy IEEE transactions on very large scale integration (VLSI) systems 19 (12 …, 2010 | 23 | 2010 |
| Time-based all-digital technique for analog built-in self-test R Vasudevamurthy, PK Das, B Amrutur IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (2), 334-342, 2013 | 12 | 2013 |
| A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test R Vasudevamurthy, PK Das, B Amrutur 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2035-2038, 2011 | 9 | 2011 |
| Multiphase technique to speed-up delay measurement via sub-sampling R Vasudevamurthy, B Amrutur 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 2 | 2013 |
| Pulse-width Modulation Technique for Generation of Multiple Analog Voltages for On-chip Calibration R Vasudevamurthy 2022 35th International Conference on VLSI Design and 2022 21st …, 2022 | | 2022 |
| Dravidianism and the Cultural Fabric of India & South-East Asia R Vasudevamurthy | | 2017 |
| Śāstras—an impediment to progress? R Vasudevamurthy ŚĀSTRA-S THROUGH THE LENS OF WESTERN INDOLOGY, 119, 2016 | | 2016 |
| System and method for built-in self test (bist) in an integrated circuit R VASUDEVAMURTHY, B Amrutur | | 2014 |
Bharadwaj AmruturIndian Institute of ScienceVerified email at iisc.ac.in
