| Method and structure for cooling a dual chip module with one high power chip AR Arvelo, KK Sikka, HT Toy US Patent 7,031,162, 2006 | 113 | 2006 |
| Segmentation of a die stack for 3D packaging thermal management AR Arvelo, EG Colgan, JH Magerlein, KC Marston, KC Rivera, KK Sikka, ... US Patent 7,928,562, 2011 | 99 | 2011 |
| Method for controlling thermal interface gap distance DL Edwards, MJ Emmett, S Iruvanti, RA Sherif, K Sikka, HT Toy US Patent 6,294,408, 2001 | 97 | 2001 |
| Enhanced thermal management of 3-D stacked die packaging GK Bartley, DR Motschman, KK Sikka, JA Wakil, X Wei, J Zheng US Patent 8,299,608, 2012 | 84 | 2012 |
| Analysis and optimization of a natural draft heat sink system TS Fisher, KE Torrance, KK Sikka InterSociety Conference on Thermal Phenomena in Electronic Systems, I-THERM …, 1996 | 55 | 1996 |
| Modeling of vapor chamber as heat spreading devices X Wei, K Sikka Thermal and Thermomechanical Proceedings 10th Intersociety Conference on …, 2006 | 52 | 2006 |
| Microjet module assembly RJ Bezama, G Natarajan, KK Sikka, HT Toy US Patent 7,516,776, 2009 | 45 | 2009 |
| Multi-objective optimization of a chip-attached micro pin fin liquid cooling system V Radmard, Y Hadad, S Rangarajan, CH Hoang, N Fallahtafti, CL Arvin, ... Applied Thermal Engineering 195, 117187, 2021 | 41 | 2021 |
| Chip package having chip extension and method EG Colgan, DL Edwards, BV Fasano, KK Sikka, JA Zitz, W Zou US Patent 7,250,576, 2007 | 41 | 2007 |
| Microjet module assembly RJ Bezama, G Natarajan, KK Sikka, HT Toy US Patent 7,992,627, 2011 | 38 | 2011 |
| Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging VR Jadhav, DL Questad, KK Sikka, X Wei, J Zheng US Patent 7,812,438, 2010 | 38 | 2010 |
| Heat sinks with fluted and wavy plate fins in natural and low-velocity forced convection KK Sikka, KE Torrance, CU Scholler, PI Salanova IEEE Transactions on Components and Packaging Technologies 25 (2), 283-292, 2002 | 38 | 2002 |
| An analytical temperature prediction method for a chip power map KK Sikka Semiconductor Thermal Measurement and Management IEEE Twenty First Annual …, 2005 | 35 | 2005 |
| Direct bonded heterogeneous integration (DBHi) Si bridge K Sikka, R Bonam, Y Liu, P Andry, D Parekh, A Jain, M Bergendahl, ... 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 136-147, 2021 | 34 | 2021 |
| Multichip module with stiffening frame and associated covers S Li, GB Monjeau, KK Sikka, HT Toy, T Weiss US Patent 9,089,051, 2015 | 33 | 2015 |
| Lid edge capping load M Beaumier, M Belazzouz, PJ Brofman, DL Edwards, KK Sikka, J Zheng, ... US Patent 7,733,655, 2010 | 33 | 2010 |
| Direct bonded heterogeneous integration packaging structures KK Sikka, JA Casey, J Rubin, A Kumar, D Gupta, CL Arvin, ... US Patent 10,580,738, 2020 | 31 | 2020 |
| Multi-chip package structures with discrete redistribution layers JM Rubin, KK Sikka, SL Wright, LA Clevenger US Patent 11,164,817, 2021 | 30 | 2021 |
| An efficient lid design for cooling stacked flip-chip 3D packages K Sikka, J Wakil, H Toy, H Liu 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in …, 2012 | 29 | 2012 |
| Thermally efficient semiconductor chip KK Sikka, JU Knickerbocker, SL Shinde US Patent 6,292,367, 2001 | 27 | 2001 |
Shidong LiIBM, University at Buffalo, Tongji UniversityVerified email at us.ibm.com
