Chitrakant Sahu
TitleCited byYear
Charge-plasma based process variation immune junctionless transistor
C Sahu, J Singh
IEEE Electron Device Letters 35 (3), 411-413, 2014
Potential benefits and sensitivity analysis of dopingless transistor for low power applications
C Sahu, J Singh
IEEE transactions on electron devices 62 (3), 729-735, 2015
PVT-aware design of dopingless dynamically configurable tunnel FET
A Lahgere, C Sahu, J Singh
IEEE Transactions on Electron Devices 62 (8), 2404-2409, 2015
Design and performance projection of symmetric bipolar charge-plasma transistor on SOI
C Sahu, A Ganguly, J Singh
Electronics Letters 50 (20), 1461-1463, 2014
Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications
A Lahgere, C Sahu, J Singh
Electronics Letters 51 (16), 1284-1286, 2015
Device and circuit performance analysis of double gate junctionless transistors atLg= 18 nm
C Sahu, J Singh
The Journal of Engineering 2014 (3), 105-110, 2014
Temperature sensitivity analysis of dopingless charge-plasma transistor
V Shrivastava, A Kumar, C Sahu, J Singh
Solid-State Electronics 117, 94-99, 2016
Simplified drain current model for pinch-off double gate junctionless transistor
C Sahu, P Swami, S Sharma, J Singh
Electronics Letters 50 (2), 116-118, 2014
A highly linear RF mixer using gate-all-around junctionless transistor
S Pandey, C Sahu, J Singh
International Journal of Electronics Letters 5 (2), 129-136, 2017
Linearly separable pattern classification using memristive crossbar circuits
K Singh, C Sahu, J Singh
Fifteenth International Symposium on Quality Electronic Design, 323-329, 2014
SiGe source charge plasma TFET for biosensing applications
N Shafi, C Sahu, C Periasamy, J Singh
2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017
Virtually doped SiGe tunnel FET for enhanced sensitivity in biosensing applications
N Shafi, C Sahu, C Periasamy
Superlattices and Microstructures 120, 75-89, 2018
A dynamically configurable silicon nanowire field effect transistor based on electrically doped source/drain
C Sahu, A Lahgere, J Singh
arXiv preprint arXiv:1412.4975, 2014
Characteristics of gate inside junctionless transistor with channel length and doping concentration
P Kumar, C Sahu, A Shrivastava, PN Kondekar
2013 IEEE International Conference of Electron Devices and Solid-state …, 2013
Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor
C Sahu, J Singh
Journal of Computational Electronics 15 (1), 53-60, 2016
Biosensing performance optimization of DMFET for fully filled and partially filled cavity
A Porwal, C Sahu
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 281-286, 2018
VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder
AM Joshi, MS Ansari, C Sahu
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018
Analog/RF performance comparison of junctionless and dopingless field effect transistor
C Sahu, JS Parmar
2017 International Conference on Computer, Communications and Electronics …, 2017
Subthreshold Analog/RF performance estimation of doping-less DGFET for ULP applications
A Kumar, C Sahu, J Singh
2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-4, 2014
Electrical characteristics and short channel performance comparison of different gate junctionless transistors
C Sahu, J Singh, PN Kondekar
2013 International Conference on Control, Automation, Robotics and Embedded …, 2013
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