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SUMALYA GHOSH, PhD
SUMALYA GHOSH, PhD
Lead Engineer, Sankalp Semiconductor (An HCL Technologies Company)
Verified email at phd.nitdgp.ac.in
Title
Cited by
Cited by
Year
Symbiotic Organisms Search Algorithm for Optimal Design of CMOS Two-stage Op-amp with Nulling Resistor and Robust Bias Circuit
S Ghosh, BP De, R Kar, AK Mal
IET Circuits, Devices & Systems 13 (5), 679-688, 2019
122019
Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach
S Ghosh, BP De, R Kar, D Mandal, AK Mal
Computers & Electrical Engineering 80, 1-19, 2019
92019
Fast and Optimized Design of a Differential VCO using Symbolic Technique and Multi Objective Algorithms
M Panda, SK Patnaik, AK Mal, S Ghosh
IET Circuits, Devices & Systems 13 (8), 1187-1195, 2019
92019
Optimal Design Of 5.5 GHz Low Power, High Gain CMOS LNA Using Flower Pollination Algorithm
S Ghosh, BP De, R Kar, D Mandal, AK Mal
Journal of Computational Electronics 18 (2), 737-747, 2019
72019
Optimal Design Of Ultra-Low-Power 2.4 GHz LNA For IEEE 802.15.4/Bluetooth Applications
S Ghosh, BP De, KB Maji, R Kar, D Mandal, AK Mal
Journal of Circuits, Systems, and Computers 29 (16), 2050261-1-2050261-19, 2020
52020
Voltage-Controlled Ring Oscillator for Harmonic Frequency Generation
S Mal, AK Mal, S Ghosh
Intelligent Computing and Applications, 277-286, 2015
52015
Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) MOSFET using Simplex-PSO Algorithm
D Chowdhury, BP De, KB Maji, S Ghosh, R Kar, D Mandal
2019 Devices for Integrated Circuit (DevIC), 334-336, 2019
32019
An Evolutionary-based Design Methodology for Performance Enhancement of a Folded-Cascode OTA using Symbiotic Organisms Search Algorithm and gm/ID Technique
M Panda, SK Patnaik, AK Mal, S Ghosh
Analog Integrated Circuits and Signal Processing 105 (2), 215-227, 2020
22020
Design of Low-Noise Amplifier with High CMRR for Sensor Application
D Jana, S Ghosh, R Krishna, S Mandal, AK Mal
Advanced Computational and Communication Paradigms, 1-10, 2018
22018
Optimization of Subthreshold Parameters for Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET Using Craziness-Based Particle Swarm Optimization Algorithm
D Chowdhury, BP De, KB Maji, S Ghosh, R Kar, D Mandal, S Bhunia
Lecture Notes in Electrical Engineering 602, 203-211, 2019
2019
Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) Mosfet Using PSO Variants
D Chowdhury, BP De, KB Maji, SGR Kar, D Mandal, S Bhunia
International Journal of Nanoscience, 2019
2019
Analog amplifier design in short-channel MOSFET using alpha-power model
S Ghosh, S Mal, AK Mal
2015 2nd International Conference on Electronics and Communication Systems …, 2015
2015
Amplifier Design Optimization in CMOS
S Ghosh, AK Mal, S Mal
Intelligent Computing and Applications, 287-297, 2015
2015
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