| High density and low leakage current based SRAM cell using 45 nm technology S Akashe, S Sharma International Journal of Electronics 100 (4), 536-552, 2013 | 36 | 2013 |
| Low power memristor based 7T SRAM using MTCMOS technique VS Baghel, S Akashe 2015 Fifth International Conference on Advanced Computing & Communication …, 2015 | 33 | 2015 |
| Design and analysis of CMOS ring oscillator using 45 nm technology V Sikarwar, N Yadav, S Akashe 2013 3rd IEEE International Advance Computing Conference (IACC), 1491-1495, 2013 | 33 | 2013 |
| Leakage current reduction techniques for 7T SRAM cell in 45 nm technology S Akashe, S Sharma Wireless personal communications 71, 123-136, 2013 | 30 | 2013 |
| A novel high speed & power efficient half adder design using MTCMOS Technique in 45 nanometre regime S Akashe, NK Tiwari, J Shrivas, R Sharma 2012 IEEE international conference on advanced communication control and …, 2012 | 30 | 2012 |
| Reduction of leakage current and power in full subtractor using MTCMOS technique M Gautam, S Akashe 2013 International Conference on Computer Communication and Informatics, 1-4, 2013 | 27 | 2013 |
| Designing and simulation of full adder cell using FINFET technique R Saraswat, S Akashe, S Babu 2013 7th International Conference on Intelligent Systems and Control (ISCO …, 2013 | 27 | 2013 |
| High performance, low power 200 Gb/s 4: 1 MUX with TGL in 45 nm technology M Mishra, S Akashe Applied Nanoscience 4 (3), 271-277, 2014 | 23 | 2014 |
| Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology N Yadav, S Khandelwal, S Akashe 2013 International Conference on Control, Computing, Communication and …, 2013 | 23 | 2013 |
| Optimization of leakage current in SRAM cell using shorted gate DG FinFET V Sikarwar, S Khandelwal, S Akashe 2013 Third International Conference on Advanced Computing and Communication …, 2013 | 23 | 2013 |
| Analysis of power in 3T DRAM and 4T DRAM cell design for different technology S Akashe, A Mudgal, SB Singh 2012 World Congress on Information and Communication Technologies, 18-21, 2012 | 23 | 2012 |
| Modeling and analysis of low power 10 T full adder with reduced ground bounce noise R Singh, S Akashe Journal of Circuits, Systems, and Computers 23 (01), 1450005, 2014 | 22 | 2014 |
| Performance analysis of gate-all-around field effect transistor for CMOS nanoscale devices A Sharma, S Akashe International Journal of Computer Applications 84 (10), 44-48, 2013 | 21 | 2013 |
| A low-leakage current power 45-nm CMOS SRAM S Akashe, DK Sinha, S Sharma Indian Journal of Science and Technology, 440-442, 2011 | 21 | 2011 |
| High density and low leakage current based 5T SRAM cell using 45 nm technology S Akashe, S Bhushan, S Sharma Romanian journal of information science and technology 15 (2), 155-168, 2012 | 20 | 2012 |
| Supply voltage minimization techniques for SRAM leakage reduction S Khandelwal, S Akashe, S Sharma Journal of computational and theoretical nanoscience 9 (8), 1044-1048, 2012 | 19 | 2012 |
| Analysis of leakage reduction technique on different SRAM cells M Yadav, S Akashe, Y Goswami International Journal of Engineering Trends and Technology 2 (3), 78-83, 2011 | 19 | 2011 |
| Analysis and optimization of active power and delay of 10T full adder using power gating technique at 45 nm technology R Gupta, SP Pandey, S Akashe, A Vidyarthi IOSR Journal of VLSI and Signal Processing 2 (1), 51-57, 2013 | 18 | 2013 |
| Design low power 10T full adder using process and circuit techniques S Mishra, SS Tomar, S Akashe 2013 7th International Conference on Intelligent Systems and Control (ISCO …, 2013 | 17 | 2013 |
| Design and performance analysis of 1 bit full adder using GDI technique in nanometer era J Shrivas, S Akashe, N Tiwari 2012 World Congress on Information and Communication Technologies, 822-825, 2012 | 17 | 2012 |
