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M.vinodhini
M.vinodhini
Verified email at blr.amrita.edu
Title
Cited by
Cited by
Year
Error detection and correction in semiconductor memories using 3D parity check code with hamming code
S Tambatkar, SN Menon, V Sudarshan, M Vinodhini, NS Murty
2017 International Conference on Communication and Signal Processing (ICCSP …, 2017
382017
Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories
P Raha, M Vinodhini, NS Murty
2017 International Conference on Computer Communication and Informatics …, 2017
212017
Reliable low power NoC interconnect
M Vinodhini, NS Murty
Microprocessors and Microsystems 57, 15-22, 2018
202018
Diagonal hamming based multi-bit error detection and correction technique for memories
GM Sai, KM Avinash, LSG Naidu, MS Rohith, M Vinodhini
2020 International Conference on Communication and Signal Processing (ICCSP …, 2020
172020
Joint crosstalk avoidance with multiple bit error correction coding technique for NoC interconnect
TS Teja, TS Kiran, TVVS Narayana, M Vinodhini, NS Murty
2018 International Conference on Advances in Computing, Communications and …, 2018
122018
Transient error correction coding scheme for reliable low power data link layer in NoC
M Vinodhini, NS Murty, TK Ramesh
IEEE Access 8, 174614-174628, 2020
112020
Reliable router architecture with elastic buffer for NoC architecture
R Louis, M Vinodhini, NS Murty
2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015
112015
Code with crosstalk avoidance and error correction for network on chip interconnects
KASS Lakshmi, AM Keerthi, KM Sri, M Vinodhini
2020 4th International Conference on Trends in Electronics and Informatics …, 2020
82020
A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance
M Vinodhini, K Lillygrace, NS Murty
2015 IEEE International Conference on Computational Intelligence and …, 2015
82015
Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches
H Kalwad, S Neeharika, S Divya, M Vinodhini, NS Murty
2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015
72015
Merged arbitration and switching techniques for network on chip router
M Vinodhini, NS Murty
2017 International conference on Microelectronic Devices, Circuits and …, 2017
62017
Multi-bit error correction coding with crosstalk avoidance using parity sharing technique for noc
S Rajagopal, M Vinodhini, NS Murty
2018 IEEE International Symposium on Smart Electronic Systems (iSES …, 2018
52018
Multi-bit low redundancy error control with parity sharing for NoC interconnects
US Himaja, M Vinodhini, NS Murty
2018 3rd International Conference on Communication and Electronics Systems …, 2018
52018
Crosstalk aware transient error correction coding technique for NoC links
M Vinodhini, NS Murty, TK Ramesh
Microelectronics Reliability 124, 114296, 2021
42021
Transition based odd/full invert coding scheme for crosstalk avoidance and low power consumption in NoC links
M Vinodhini, NS Murty
Advances in Signal and Data Processing: Select Proceedings of ICSDP 2019 …, 2021
42021
Improved High speed approximate multiplier
T Roshini, RS Krishna, PK Reddy, M Vinodhini
2020 4th International Conference on Electronics, Materials Engineering …, 2020
32020
Logic encryption of combinational circuits
K Pritika, M Vinodhini
2019 3rd International Conference on Electronics, Materials Engineering …, 2019
32019
Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques
R Manasa, G Hegde, M Vinodhini
2018 International Conference on Electrical, Electronics, Communication …, 2018
32018
Data flipping coding technique to reduce NOC link power
M Moulika, M Vinodhini, NS Murty
2017 IEEE International Conference on Computational Intelligence and …, 2017
32017
Congestion aware negative first routing with fair arbitration for network on chip
R Somisetty, VSS Karthik, MRS Srujan, M Vinodhini
2022 6th International Conference on Computing Methodologies and …, 2022
22022
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