Niranjan M Devashrayee
Niranjan M Devashrayee
Professor of Electronics & Communication Engineering
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Cited by
Cited by
Hamming distance based reordering and columnwise bit stuffing with difference vector: A better scheme for test data compression with run length based codes
US Mehla, KS Dasgupta, NM Devashrayee
2010 23rd International Conference on VLSI Design, 33-38, 2010
Run-length-based test data compression techniques: how far from entropy and power bounds?—a survey
US Mehta, KS Dasgupta, NM Devashrayee
VLSI Design 2010, 2010
Modified selective Huffman coding for optimization of test data compression, test application time and area overhead
US Mehta, KS Dasgupta, NM Devashrayee
Journal of Electronic Testing 26 (6), 679-688, 2010
Diffusivity of Al in Ti and the effect of Si doping for very large scale integrated circuit interconnect metallization
RK Nahar, NM Devashrayee, WS Khokle
Journal of Vacuum Science & Technology B: Microelectronics Processing and …, 1988
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator
V Savani, NM Devashrayee
Microelectronics journal 74, 116-126, 2018
Study the effect of dispersion of filler in polymer composite for radiation shielding
M Saiyad, NM Devashrayee, RK Mevada
Polymer composites 35 (7), 1263-1266, 2014
Effect of Si on the reaction kinetics of Ti/AlSi bilayer structures
RK Nahar, NM Devashrayee
Applied physics letters 50 (3), 130-131, 1987
High Speed PFD with Charge Pump and Loop Filter for Low Jitter and Low Power PLL 1
KP Thakore, HC Parmar, NM Devashrayee
Survey of test data compression technique emphasizing code based schemes
US Mehta, KS Dasgupta, NM Devashrayee
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
Hamming distance based 2-D reordering with power efficient don't care bit filling: optimizing the test data compression method
US Mehta, NM Devashrayee, KS Dasgupta
2010 International Symposium on System on Chip, 1-7, 2010
Low power and low jitter phase frequency detector for phase lock loop
KP Thakore, HC Parmar, NM Devashrayee
International Journal of Engineering Science and Technology 3 (3), 1998-2004, 2011
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method
U Mehta, KS Dasgupta, NM Devashrayee
VLSI Design 2011, 9, 2011
Characterization of a CMOS differential current conveyor using 0.25 micron technology
AP Naik, NM Devashrayee
International Journal of Advanced Engineering and Applications, 177-182, 2010
Analysis and design of low-voltage low-power high-speedádouble tail current dynamic latch comparator
V Savani, NM Devashrayee
Analog Integrated Circuits and Signal Processing 93 (2), 287-298, 2017
Development of Radiation Hardened by Design (RHBD) primitive gates using 0.18 μm CMOS technology
R Trivedi, NM Devashrayee, US Mehta, NM Desai, H Patel
2015 19th International Symposium on VLSI Design and Test, 1-2, 2015
The influence of stabilisers on resistance to gamma radiation for epoxy based polymeric composite material.
RKM Mamta Saiyad,N.M.Devashrayee
composites:Part B 57, Pages 71-79, 2014
Low voltage, low power folding amplifier for folding & interpolating ADC
S Oza, NM Devashrayee
2009 International Conference on Advances in Recent Technologies in …, 2009
Electrical properties of RF sputtered NiCr thin film resistors with Cu contacts
RK Nahar, NM Devashrayee
Electrocomponent Science and Technology 11, 1983
A novel low offset low power CMOS dynamic comparator
PP Gandhi, NM Devashrayee
Analog Integrated Circuits and Signal Processing 96 (1), 147-158, 2018
Suitability of various low-power testing techniques for IP core-based SoC: a survey
U Mehta, K Dasgupta, N Devashrayee
VLSI Design 2011, 2011
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