| Selection and placement of decoupling capacitors in high speed systems JN Tripathi, J Mukherjee, PR Apte, NK Chhabra, RK Nagpal, R Malik Electromagnetic Compatibility Magazine, IEEE 2 (4), 72-78, 2013 | 21 | 2013 |
| Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms JN Tripathi, NK Chhabra, RK Nagpal, R Malik, J Mukherjee 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 361-364, 2012 | 13 | 2012 |
| Maintaining power integrity by damping the cavity-mode anti-resonances' peaks on a power plane by particle swarm optimization JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee Thirteenth International Symposium on Quality Electronic Design (ISQED), 525-528, 2012 | 10 | 2012 |
| A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits JN Tripathi, J Mukherjee, PR Apte, RK Nagpal, NK Chhabra, R Malik 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging …, 2013 | 9 | 2013 |
| Die resistance-capacitance extraction and validation NK Chhabra US Patent 10,585,996, 2020 | 6 | 2020 |
| Power integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee, PR Apte International Symposium on Quality Electronic Design (ISQED), 670-675, 2013 | 6 | 2013 |
| Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm NK Chhabra, K Bhatheja, JN Tripathi, R Nagpal, R Malik 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging …, 2013 | 5 | 2013 |
| Chip power model generation using post silicon measurements NK Chhabra, PM Pawaskar, IIWH Hempy, G MATHUR US Patent App. 15/725,961, 2019 | 1 | 2019 |
| Controller architecture for reducing on-die capacitance NK Chhabra US Patent 10,896,721, 2021 | | 2021 |
| Power delivery network analysis of memory unit I/O power domain NK Chhabra, PM Pawaskar US Patent 10,691,190, 2020 | | 2020 |
| On-die decoupling capacitor area optimization NK Chhabra, R Halba, SN Mehetre US Patent 10,621,387, 2020 | | 2020 |
| Mitigation of simultaneous switching output effects NK Chhabra, HK Wadhavankar, AA Jawkar US Patent 10,594,314, 2020 | | 2020 |
| Method of signal integrity and power integrity analysis for address bus NK Chhabra, G Mathur, A Dalimkar US Patent 10,585,817, 2020 | | 2020 |
| Selection of die and package parasitic for IO power domain NK Chhabra, R Halba US Patent 10,585,999, 2020 | | 2020 |
| Probability-based optimization of system on chip (SOC) power NK Chhabra, R Halba, SK Shaw, SN Mehetre US Patent 10,560,116, 2020 | | 2020 |
| Controller architecture for reducing on-die capacitance NK Chhabra US Patent 10,541,020, 2020 | | 2020 |
| Effective Analysis Methodology for Reducing Power Management Integrated Circuit (PMIC) Coupling Noise in Mobile System DesignCon 2015, 2015 | | 2015 |
| Top Down design Methodology for Enhanced Electromagnetic Band Gap Structures JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee DesignCon 2014, 2014 | | 2014 |
| A novel EBG power plane structure for suppressing SSN in high speed systems JN Tripathi, J Mukherjee, PR Apte, RK Nagpal, NK Chhabra, R Malik Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 …, 2013 | | 2013 |
| Unconventional applications of conventional IBIS models NK Chhabra, V Goyal Electrical Performance of Electronic Packaging and Systems (EPEPS-2012), 212-215, 2012 | | 2012 |
