| Reduction of Power Dissipation in Logic Circuits DVMR Sreenivasa Rao. Ijjada International Journal of Computer Applications 24 (6), 10-14, 2011 | 15* | 2011 |
| SS< 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications AK Dharmireddy, A Sharma, MS Babu, SR Ijjada Materials Today: Proceedings, 2020 | 10 | 2020 |
| Performance analysis of Tri-gate SOI FinFET structure with various fin heights using TCAD simulations PHST Ajaykumar Dharmireddy,Sreenivasa Rao Ijjada Journal of Advanced research in Dynamical and control systems 11 (2), 1291-1298, 2019 | 10 | 2019 |
| Ijjada, Ayyanna. G, G. Sekhar Reddy, Dr. V. Malleswara Rao,“Performance of different cmos logic styles for low power and high speed” S Rao International Journal of VLSI design & Communication Systems (VLSICS) Vol 2 …, 2011 | 10 | 2011 |
| A Novel design of SOI based Fin Gate TFET A Dharmireddy, SR Ijjada 2021 2nd Global Conference for Advancement in Technology (GCAT), 1-4, 2021 | 8 | 2021 |
| Quantum-dot cellular automata technology for high-speed high-data-rate networks A Hariprasad, SR Ijjada Circuits, Systems, and Signal Processing 38, 5236-5252, 2019 | 8 | 2019 |
| Design of high efficient & low power basic gates in subthreshold region SR Ijjada, R Sirigiri, B Kumar, VM Rao International Journal of Advances in Engineering & Technology 1 (2), 215-220, 2011 | 7 | 2011 |
| A Real world system for Detection and Tracking DVMR Sreenivasa Rao. Ijjada, P.H.S.T.Murty IEEE Explorer, 939- 943, 2009 | 7* | 2009 |
| Design of MEMS Cantilever Sensors for Identification of VOCs using IntelliSuite BRK Sreenivasa Rao Ijjada Materials Today – Proceedings 22, 3162–3170, 2020 | 6* | 2020 |
| Calibration Techniques of Analog to Digital Converters(ADCs) SRI Chakradhar Adupa, Rajesh Kumar Srivastava International Journal of Innovative Technology and Exploring Engineering 8 …, 2019 | 6 | 2019 |
| SOI FinFET based 10T SRAM cell design against short channel effects D Sudha, CS Rani, SR Ijjada Acta Physica Polonica A 135 (4), 702-704, 2019 | 6 | 2019 |
| Analysis and enhancement of capacitive pressure sensor's sensitivity through material engineering processes A Madupu, A Sharma, PG Ishwari, SR Ijjada Materials Today: Proceedings 10, 2020 | 5 | 2020 |
| A 75 µW Two-Stage Op-Amp using 0.18 µm CMOS Technology for High-Speed Operations K Shasidhar, B Naresh, SR Ijjada ActaPhysica Polonica A, 1075-1077, 2019 | 5 | 2019 |
| FinFET Modelling Using TCAD SR Ijjada, C Mannepalli, M Hameed Pasha Proceedings of 2nd International Conference on Micro-Electronics …, 2018 | 5 | 2018 |
| Design of low power and high speed inverter SR Ijjada, SVS Kumar, MD Reddy, SA Rahaman, VM Rao International Journal of Distributed and Parallel Systems 2 (5), 127, 2011 | 5 | 2011 |
| Design of Low Voltage-Power: Negative capacitance Charge Plasma FinTFET for AIOT Data Acquisition Blocks A Dharmireddy, SR Ijjada 2022 International Conference on Breakthrough in Heuristics And …, 2022 | 4 | 2022 |
| Performance analysis of various Fin patterns of hybrid Tunnel FET A Dharmireddy, SR Ijjada, I Hemalatha 1st International Journal of Electrical and Electronics Research 10, 806-810, 2022 | 4 | 2022 |
| Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC CMSRI Chakradhar Adupu International Journal of Innovative Technology and Exploring Engineering 9 …, 2019 | 4* | 2019 |
| Design of a Two Stage Operational Amplifier with Zero Compensation for Accurate Bandgap Reference Circuit M Chaithanya, RK Srivastava, SR Ijjada J Acta Physica Polonica A 135 (5), 977-979, 2019 | 4 | 2019 |
| Performance of different cmos logic styles for low power and high speed I SreenivasaRao, G Ayyanna, GS Reddy, VM Rao International Journal of VLSI & Signal Processing Applications, 2011 | 4 | 2011 |
Dr.V. Malleswara RaoAndhra University, VisakhapatnamVerified email at andhrauniversity.edu.in
Dr.V. Malleswara RaoAndhra University, VisakhapatnamVerified email at andhrauniversity.edu.in