| Optimal Test Suite Selection in Regression Testing with Testcase Prioritization using modified Ann and Whale Optimization Algorithm SK Harikarthik, V Palanisamy, P Ramanathan Cluster Computing - "The Journal of Networks, Software Tools and …, 2017 | 45 | 2017 |
| A new hybrid multiplier using Dadda and Wallace method P Anitha, P Ramanathan International Conference on Electronics and Communication Systems (ICECS …, 2014 | 33 | 2014 |
| Effect of BIRADS Shape descriptors on Breast Cancer Analysis B Surendiran, P Ramanathan, A Vadivel International Journal of Medical Engineering and Informatics 7 (1), 65-79, 2015 | 19 | 2015 |
| High speed multiplier design using Decomposition Logic P Ramanathan, PT Vanathi, S Agarwal Serbian Journal of Electrical Engineering 6 (1), 33-42, 2009 | 15 | 2009 |
| A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing P Ramanathan, PT Vanathi International Journal of Recent Trends in Engineering 2 (6), 58-62, 2009 | 14 | 2009 |
| Modified Low Power Wallace Tree Multiplier Using Higher Order Compressors P Ramanathan, P Kowsalya, P Anitha International Journal of Electronics Letters 5 (2), 177-188, 2016 | 13 | 2016 |
| Hybrid prefix adder architecture for minimizing the power delay product P Ramanathan, PT Vanathi International Journal of Electrical and Computer Engineering 4, 9, 2009 | 13 | 2009 |
| Comparative Analysis and Comparison of Various AQM Algorithm for High Speed U Pujeri, V Palaniswamy, P Ramanathan, R Pujeri Indian Journal of Science and Technology 8 (35), 1-12, 2015 | 10 | 2015 |
| Comparative analysis of low power high performance flip–flops in the 0.13µm technology S Agarwal, P Ramanathan, PT Vanathi International Conference on Advanced Computing and Communications, 2007 …, 2007 | 10 | 2007 |
| Power estimation of benchmark circuits using artificial neural networks P Ramanathan, B Surendiran, PT Vanathi Pensee 75 (9), 427-433, 2013 | 9 | 2013 |
| Low Power Parallel Prefix Adder Kowsalya P, Malathi M, Ramanathan P Applied Mechanics and Materials 573, 194-200, 2014 | 6* | 2014 |
| A novel logarithmic prefix adder with minimized power delay product P Ramanathan, PT Vanathi Journal of Scientific & Industrial Research 69, 17-20, 2010 | 6 | 2010 |
| Area Efficient Carry Select Adder using Negative Edge Triggered Flip-Flop P Ramanathan, P Anitha Applied Mechanics and Materials 573, 187-193, 2014 | 4* | 2014 |
| Decomposition algorithm for power delay product optimization in Wallace multiplier P Ramanthan, PT Vanathi, C Amaresh, N Senthil Raja International Conference on Control, Automation, Communication and Energy …, 2009 | 4 | 2009 |
| Innovative localization algorithm using the line of intersection technique in Wireless Sensor Networks T Mythili, J Ramesh, P Ramanathan Journal of Internet Technology 21 (No.2), 425-433, 2020 | 3 | 2020 |
| Indoor Channel Characterization with Multiple Hypotheses Testing in Massive Multiple Input Multiple Output VC Prakash, G Nagarajan, P Ramanathan Journal of Computational and Theoretical Nanoscience 16, 1-5, 2019 | 3 | 2019 |
| Modified Low-Power Built-in Self-test for Image Processing Application P Anitha, P Ramanathan, PT Vanathi Lecture Notes in Computational Vision and Biomechanics, Computer Aided …, 2019 | 2 | 2019 |
| Synthesis of High Speed Vedic Multiplier S Nithyadevi, B Gopinath, P Ramanathan International Journal of Applied Engineering Research 10 (29), 22614-22617, 2015 | 2* | 2015 |
| A Compact Sierpinski Gasket Fractal Antenna for S, C, X, and Ku Band Applications PR Ezhumalai Aravindraj, Ganesan Nagarajan Progress In Electromagnetics Research C 141, 33-40, 2024 | 1* | 2024 |
| Enhancement of Regression Testing using Genetic Data Generation and Test Case Prioritization using m-ACO Technique SK Harikarthik, P Ramanathan, V Palanisamy International Journal of Engineering and Technology 7 (13), 95-99, 2018 | 1 | 2018 |
Vanathi PrabahkarPSG College of TechnologyVerified email at ece.psgtech.ac.in
