| High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell J Kandpal, A Tomar, M Agarwal, KK Sharma IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 72 | 2020 |
| A new design of low power high speed hybrid CMOS full adder M Agarwal, N Agrawal, MA Alam 2014 international conference on signal processing and integrated networks …, 2014 | 37 | 2014 |
| Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications J Kandpal, A Tomar, M Agarwal Microelectronics Journal 115, 105205, 2021 | 13 | 2021 |
| Architecture of a real‐time delay calculator for digital beamforming in ultrasound system M Agarwal, A De, S Banerjee IET Circuits, Devices & Systems 10 (4), 322-329, 2016 | 6 | 2016 |
| An IEEE single-precision arithmetic based beamformer architecture for phased array ultrasound imaging system M Agarwal, A Tomar, N Kumar Engineering Science and Technology, an International Journal 24 (5), 1080-1089, 2021 | 5 | 2021 |
| An IEEE single precision floating point arithmetic-based apodization architecture for portable ultrasound imaging system M Agarwal, A De, S Banerjee IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2275-2287, 2019 | 3 | 2019 |
| VLSI architecture for IEEE single precision floating point moving average calculator M Agarwal, A Mishra, S Banerjee 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), 1-4, 2017 | 3 | 2017 |
| High performance 20-T based hybrid full adder using 90nm CMOS technology J Kandpal, A Tomar, K Pandey, M Agarwal 2019 Women Institute of Technology Conference on Electrical and Computer …, 2019 | 1 | 2019 |
| A Hardware Efficient Beamformer for Real-Time Convex Array based Ultrasound Imaging System M Agarwal IIT Kharagpur, 2018 | | 2018 |
