Chita R. Das
TitleCited byYear
Towards characterizing cloud backend workloads: insights from Google compute clusters
AK Mishra, JL Hellerstein, W Cirne, CR Das
ACM SIGMETRICS Performance Evaluation Review 37 (4), 34-41, 2010
3632010
ViChaR: A dynamic virtual channel regulator for network-on-chip routers
CA Nicopoulos, D Park, J Kim, N Vijaykrishnan, MS Yousif, CR Das
Proceedings of the 39th Annual IEEE/ACM International Symposium on …, 2006
3482006
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ...
ACM SIGARCH Computer Architecture News 35 (2), 138-149, 2007
3022007
A low latency router supporting adaptivity for on-chip interconnects
J Kim, D Park, T Theocharides, N Vijaykrishnan, CR Das
Proceedings. 42nd Design Automation Conference, 2005., 559-564, 2005
2912005
Exploring fault-tolerant network-on-chip architectures
D Park, C Nicopoulos, J Kim, N Vijaykrishnan, CR Das
International Conference on Dependable Systems and Networks (DSN'06), 93-104, 2006
2742006
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das
DAC Design Automation Conference 2012, 243-252, 2012
2612012
A gracefully degrading and energy-efficient modular router architecture for on-chip networks
J Kim, C Nicopoulos, D Park, V Narayanan, MS Yousif, CR Das
ACM SIGARCH Computer Architecture News 34 (2), 4-15, 2006
2612006
Cooperative cache-based data access in ad hoc networks
G Cao, L Yin, CR Das
Computer 37 (2), 32-39, 2004
2582004
MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
2008 International Symposium on Computer Architecture, 251-261, 2008
2492008
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
A Jog, O Kayiran, N Chidambaram Nachiappan, AK Mishra, MT Kandemir, ...
ACM SIGPLAN Notices 48 (4), 395-406, 2013
2482013
Neither more nor less: optimizing thread-level parallelism for GPGPUs
O Kayıran, A Jog, MT Kandemir, CR Das
Proceedings of the 22nd international conference on Parallel architectures …, 2013
2322013
Aérgia: exploiting packet latency slack in on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
ACM SIGARCH computer architecture news 38 (3), 106-116, 2010
2122010
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
R Das, S Eachempati, AK Mishra, V Narayanan, CR Das
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
2122009
Application-aware prioritization mechanisms for on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
2082009
MDCSim: A multi-tier data center simulation, platform.
SH Lim, B Sharma, G Nam, EK Kim, CR Das
CLUSTER 31, 1-9, 2009
1772009
Modeling and synthesizing task placement constraints in Google compute clusters
B Sharma, V Chudnovsky, JL Hellerstein, R Rifaat, CR Das
Proceedings of the 2nd ACM Symposium on Cloud Computing, 3, 2011
1752011
Orchestrated scheduling and prefetching for GPGPUs
A Jog, O Kayiran, AK Mishra, MT Kandemir, O Mutlu, R Iyer, CR Das
ACM SIGARCH Computer Architecture News 41 (3), 332-343, 2013
1722013
Hypercube communication delay with wormhole routing
J Kim, CR Das
IEEE Transactions on Computers 43 (7), 806-814, 1994
1491994
Design and analysis of an NoC architecture from performance, reliability and energy perspective
J Kim, D Park, C Nicopoulos, N Vijaykrishnan, CR Das
2005 Symposium on Architectures for Networking and Communications Systems …, 2005
1342005
A case for heterogeneous on-chip interconnects for CMPs
AK Mishra, N Vijaykrishnan, CR Das
ACM SIGARCH Computer Architecture News 39 (3), 389-400, 2011
1242011
The system can't perform the operation now. Try again later.
Articles 1–20