| Optimized DL-TFET design for enhancing its performance parameters by using different engineering methods M Sharma, R Narang, M Saxena, M Gupta IETE Technical Review 38 (4), 429-437, 2021 | 6 | 2021 |
| Comparative study of InGaN and InGaAs based dopingless TFET with different gate engineering techniques M Sharma, R Narang, M Saxena, M Gupta Advances in Natural Sciences: Nanoscience and Nanotechnology 10 (3), 035009, 2019 | 6 | 2019 |
| Investigation of gate all around junctionless nanowire transistor with arbitrary polygonal cross section M Sharma, M Gupta, R Narang, M Saxena 2018 4th International Conference on Devices, Circuits and Systems (ICDCS …, 2018 | 6 | 2018 |
| Modeling and simulation-based investigation of 2-D symmetric double gate dopingless-TFET and its circuit performance for low-power applications M Sharma, R Narang, M Saxena, M Gupta IETE Technical Review 39 (4), 838-849, 2022 | 5 | 2022 |
| Effect of interface charges on InGaN and InGaAs based dopingless TFET and its Circuit analysis M Sharma, R Narang, M Saxena, M Gupta 2020 5th IEEE International Conference on Emerging Electronics (ICEE), 1-4, 2020 | 4 | 2020 |
Rakhi NarangSri Venkateswara College, University of DelhiVerified email at svc.ac.in
