Loading...
The system can't perform the operation now. Try again later.
Citations per year
Duplicate citations
The following articles are merged in Scholar. Their
combined citations
are counted only for the first article.
Merged citations
This "Cited by" count includes citations to the following articles in Scholar. The ones marked
*
may be different from the article in the profile.
Add co-authors
Co-authors
Follow
New articles by this author
New citations to this author
New articles related to this author's research
Email address for updates
Done
My profile
My library
Metrics
Alerts
Settings
Sign in
Sign in
Get my own profile
Cited by
All
Since 2019
Citations
2
2
h-index
1
1
i10-index
0
0
Follow
Aditya Anirudh Jonnalagadda
BITS Pilani
Verified email at hyderabad.bits-pilani.ac.in
VLSI Design
Approximate Computing
Computer Architecture
FPGA design
Deep Neural Networks
Articles
Cited by
Title
Sort
Sort by citations
Sort by year
Sort by title
Cited by
Cited by
Year
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks
AA Jonnalagadda, UA Kumar, R Thotli, S Sardesai, S Veeramachaneni, ...
IEEE Access 12, 31036-31046
, 2024
1
2024
Design of energy efficient posit multiplier
AA Jonnalagadda, AK Uppugunduru, S Veeramachaneni, SE Ahmed
Proceedings of the Great Lakes Symposium on VLSI 2023, 645-651
, 2023
1
2023
Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic
AA Jonnalagadda, R Thotli, S Veeramachaneni, UA Kumar, SE Ahmed
IEEE Embedded Systems Letters
, 2024
2024
The system can't perform the operation now. Try again later.
Articles 1–3
Show more
Privacy
Terms
Help
About Scholar
Search help
